Voltage Source Inverter Drive Using Error-compensated Pulse Width Modulation

Abstract

An error-compensated pulse width modulator (ECPWM) is proposed to improve the baseband harmonic performance and the switching loss of voltage source inverters (VSIs). Selecting between harmonic distortion and switching loss is a design tradeoff in the conventional space vector pulse width modulation. In this work, an accumulated difference in produced and desired phase voltages is considered to adjust the reference signal. This mechanism can compensate for the voltage error in the previous carrier period. With error compensation every half-carrier period, the proposed ECPWM allows one-half reduction in carrier frequency without scarifying baseband harmonic distortion. The proposed modulator is applied to a three-phase VSI with R-L load and a motor-speed-control system for experiments. The measured efficiency and operating temperature of switches confirm the effectiveness of the proposed scheme.

I. INTRODUCTION

Voltage source inverters (VSIs) are widely utilized in driving variable-speed alternating current motors. Sine-triangle pulse width modulation (PWM), space vector PWM (SVPWM), and discontinuous PWM (DPWM) are common real-time approaches to generate the driving signals for VSIs. Extensive discussions of these PWMs indicate that these PWMs can be unified by shifting efficient conducting time [1], changing modulation signals [2], or using different zero-vector distributions [3]. Therefore, a simple carrier-based implementation architecture can be used to have all the advantages of modulators, that is, simple implementation, extended linear modulation index, and 33% of switching number reduction.

Linear modulation range, implementation simplicity, power efficiency, and harmonic distortion are important factors in the control of VSIs. The tradeoff between switching loss and harmonic distortion remains a critical design issue. Several PWM techniques are discussed to reduce distortion given a fixed switching frequency [4]–[10]. For example, the extended-state observer-based control scheme [9] is proposed to reduce current harmonics. The interleaved PWM is suggested to reduce output current ripple [10]. The filtered PWM [6] is shown to attenuate baseband harmonics, especially for small modulation index reference. The novel selective harmonic elimination-based multi-module PWM [5], the multi-rate repetitive control PWM [7], the three-stage hybrid modulator [8], and the immune algorithm-based SVPWM [4] are applied to reduce voltage harmonic distortion.

A different effective time placement is used in a dual-inverter-fed open-end winding induction motor [11] to limit switching power loss. A modified finite-step predictive torque control is proposed in [12] to improve inverter loss by reducing switching frequency and calculation time. In [13], an adaptive feedback controller is developed to produce flux reference with optimized energy consumption of the induction motor. The modified phase disposition PWM is applied to a flying capacitor inverter for voltage balancing and efficiency improving [14].

A novel inverter topology is proposed to reduce switching loss and harmonic distortion [15]. The synchronized DPWM [16] is used in the application of a high-power, three-level VSI with lagging loads. Several novel DPWMs with double injections are analyzed in [17] to obtain minimum current harmonic or minimum switching loss. A feedback quantization modulator [18] is applied to a permanent-magnet synchronous motor (PMSM) drive system to show a 33% reduction in switching number in contrast to SVPWM in [19]. The minimum-switching-loss PWM proposed in [20] can reduce up to 36% of switching loss. However, the result in [17] shows that different switching strategies must be applied to achieve minimum distortion or minimum switching loss. The methods in [18], [20] involve complicated calculation to produce switching signals that will influence the applicability of modulators. In this work, a simple approach based on error compensation and asymmetric pulse width production is suggested to achieve 50% of switching number reduction without sacrificing baseband harmonic distortion.

Several different asymmetrical switching signal production methods have been proposed recently. For example, [21] produces random pulse-position-switching commands by adopting varying rising/falling slopes of triangular wave to reduce the carrier harmonic and acoustic noise of a motor drive. The asymmetrical pulse gives an additional degree of freedom when selective harmonic elimination [22] or bee colony optimization [23] is used. All the asymmetrical PWMs in [21]–[23] focus on declining harmonics only.

In this work, both baseband harmonic distortion and switching loss are considered. The simplest way to reduce switching loss is to reduce switching number, that is, to reduce carrier frequency. However, baseband harmonic distortion increases with reduced carrier frequency when the conventional SVPWM is applied. This study proposes an error-compensated pulse width modulator (ECPWM). Different references are applied for the rising and falling edges of the carrier by voltage error compensation at a rate of twice of the carrier frequency. This mechanism can greatly improve baseband harmonics and achieves a comparable performance by using only half of the switching frequency in contrast to SVPWM. Therefore, the ECPWM reduces switching loss by using a low carrier frequency without sacrificing baseband harmonic distortion.

In the simulation, a three-phase VSI with R–L load is built in PSIM. Comparisons of the phase voltages and the phase currents produced by SVPWM and the proposed modulator are shown. An experimental platform based on field-oriented control (FOC) is built to drive a PMSM to verify the reliability, applicability, and effectiveness of the proposed modulator. The switching number and harmonic distortion of the produced phase currents are illustrated. Closed-loop performances, such as motor speed and output torque, are also measured. Under the condition that the switching number of the proposed modulator is half that of SVPWM, the results indicate that the system efficiency and the operating temperature of power metal oxide semiconductor field-effect transistors (MOSFETs) are improved.

The remainder of this paper is organized as follows: Section II provides the mathematical formulation of the proposed modulator and the mechanism of reference adjustment. Section II shows the system analysis. Sections III and IV present the simulations and experiments, respectively. Finally, Section V concludes this paper.

 

II. ECPWM

A. Objectives of Modulation

For the three-phase VSI system depicted in Fig. 1, the objective is to decide the on/off status of six switches to produce desired phase voltage on the load, [VaN VbN VcN]T. If the on (off) status of the upper switch is denoted as +1 (0), then the switching state of the three-phase VSI system can be represented by a switching vector, [s1 s2 s3]T, which has elements that belong to the set {0, 1}. Therefore, the instantaneous phase voltage (normalized to Vdc) can be obtained from Equ. (1).

Fig. 1.Three-phase VSI topology.

By considering the duty ratios for each phase lag, we express the normalized mean voltage produced within each carrier cycle as Equ. (2) according to Equ. (1).

where α1, α2, α3 ∈ [0 1] are the duty ratios for phase lags. Under analog implementation, the values of α1, α2, α3 can be selected arbitrarily within the range [0 1]. However, for the digital implementation with carrier frequency fc and pulse bit resolution b -bit, the minimum pulse width that can be produced is 1/(fc × 2b) s, and a master clock frequency of (fc × 2b) Hz is required. The produced duty ratios are limited to be integer multiples of 2-b , that is, they must belong to the set {0, 1/2b, 2/2b, ⋯, (2b-1)/2b, 1}. Thus, voltage deviation is unavoidable with a finite pulse width resolution. The voltage error, although small within each carrier period, will accumulate and induce considerable current harmonics [24]. Therefore, the objective of the switching signal generation is to decide the duty ratios α1, α2, α3 ∈ [0 1] such that the accumulated voltage error is compensated for within every carrier period, that is, minimizing the difference in the desired and the produced voltage signals.

B. Error Compensation

For future reference, the input three-phase voltages, denoted as r(k)=[r1(k) r2(k) r3(k)]T, are normalized with respect to direct current (DC)-link voltage Vdc . For a given duty ratio, [α1(k) α2(k) α3(k)]T, the produced phase voltage is Sc [α1 α2 α3]T. Therefore, the difference between the reference input and the produced phase voltage is in the form

where qb{y} is the quantization that ensures y belongs to the set {0, 1/2b, 2/2b, ⋯, (2b-1)/2b, 1}. To compensate for the error in Equ. (3), the duty ratio is adjusted according to minimizing the effect of accumulated error, e(k), which is the accumulated difference in the desired and the produced phase voltages, that is,

Therefore, the duty ratio is obtained by minimizing e(k) in Equ. (4). Equ. (4) implies that switching commands are influenced by input r(k) and previous error signal e(k-1). The duty ratio can be obtained accordingly by solving the matching problem given below.

C. Duty Ratios for Error Compensation

Eigenvalue decomposition is applied to find the duty ratios that satisfy Equ. (5), that is, Equ. (5a) is written as

where vi, i =1, 2, 3 are the eigenvectors of Sc , and

Given that the matrix [v1 v2 v3] is orthonormal, Equ. (6) can be written as

which implies that

To have a solution in Equ. (8), the in the left-hand side of Equ. (8) must be zero. The equation = 0 is proven in Appendix A. Considering the matching equation in Equ. (9), is a solution regardless of the constraint αi ∈ [0 1].

A modified solution, as shown in Equ. (10), can be applied to have feasible duty ratios. Given that and Equ. (9) still holds when the duty ratios in Equ. (10) are used.

λ is a real number and is selected to ensure that the values of duty ratios αi are feasible. One selection of λ is to set it to be multiplied with the minimum value among the elements in d(k). The injection of λ will not influence the produced phase voltage when the y-connected load with an isolated neutral point is applied. The block diagram for quantization error compensation is shown in Fig. 2. The output q{α(k)} is the corresponding phase duties that are used to produce switching commands.

Fig. 2.Block diagram of quantization error compensation.

D. System Analysis

Proposition 1: Given a reference r=[r1 r2 r3]T satisfying r1+r2+r3 = 0, the duty ratios produced by Equs. (10), (5b), and (4) for a three-phase VSI can compensate for the voltage error of each phase.

[Proof] Considering the duty ratios produced for the present input r(k) and using Equs. (10) and (5b), duty ratios can be written as

By substituting Equ. (11) into Equ. (4), we can write

We define the error Δb(k) as the difference between the desired and the produced duty ratios within a carrier period, namely,

Equ. (12) can then be rewritten as Equ. (14), applying that Sc v1 = 0 , Sce(k) = e(k), and Scr(k) = r(k).

The right-hand side of Equ. (14) is the error mapping by the matrix Sc . The voltage error appears on the Y-connected phases. Therefore, Equ. (14) implies that with the duty ratios produced by Equ. (10), the error signal e(k) is the voltage deviation on the phases. From Equ. (5b), this deviation is used to adjust the reference during the subsequent carrier period to produce duty ratios. Therefore, a single cycle is sufficient for the algorithm to cancel the voltage error. However, the voltage reference and the quantization error are not constant, that is, at any iteration, a residual voltage error exists. The phase voltage deviation produced during the previous carrier period is compensated for by applying one cycle delay tracking of the reference voltage, as shown in Equs. (10), (5b), and (4).

E. Asymmetric Pulse Production

The rate of error compensation is selected to be twice the carrier frequency to improve the quality of the produced phase voltage. In this setting, given a carrier frequency fc , the reference, r(k1) , and the duty ratios, [α1(k1) α2(k1) α3(k1)]T, are updated at a rate 2fc , that is, the signals to be compared with triangular wave during rising and falling edges are different. k1 corresponds to the index of period 1/(2fc), whereas k corresponds to the index of period 1/fc.

Proposition 2: A three-phase VSI modulator with carrier frequency fc can compensate for errors every half-carrier period for the regular sampled reference r(k1)=[r1(k1) r2(k1) r3(k1)]T (sampled at the frequency 2fc ) when the duty ratio for each reference r(k1) is selected as

and λ1 is the minimum value among the elements in d(k).

[Proof] The error Δb(k1) is defined as the difference between the desired and the produced duty ratios during k1 -th half-carrier period, that is,

By substituting Equs. (15), (16), and (18) into Equ. (17), we can write

Equ. (19) states that the error signal, e(k1), is the voltage deviation in the Y-connected load. This error signal is compensated for by adjusting the reference of the subsequent half-carrier period as [see Equ. (16)]

Therefore, the proposed three-phase VSI modulator can compensate for voltage errors every half-carrier period.

 

III. SIMULATION RESULTS

To confirm the effectiveness of the proposed ECPWM, the conventional SVPWM and the proposed ECPWM are implemented by visual C++, and the three-phase VSI with R–L load is built by PSIM. The resistance (inductance) of the load is 10 Ω (15 mH). The DC-link voltage is 15 V.

The 50 Hz sinusoidal wave with a normalized amplitude of 0.5 is sampled at 8 kHz and applied to the modulators (SVPWM and ECPWM) to produce gating signals. The carrier frequency of SVPWM (ECPWM) is set as 8 kHz (4 kHz), and the pulse bit resolution of both modulators is 10.

The gating signals for the first phase lag and the produced phase voltages/currents for both modulators are shown in Figs. 3 and 4. The phase voltages produced by the ECPWM and the SVPWM are comparable by using half of the switching number in the ECPWM. The frequency components of the produced phase voltage and the phase current are shown in Figs. 5–8 to analyze baseband harmonic distortion. The baseband harmonics of the voltage/current produced by the ECPWM are reduced by using only half of the switching frequency in contrast to those produced by the SVPWM.

Fig. 3.Simulation results for the SVPWM (upper: gating signal for the first phase lag, middle: produced phase voltage, lower: produced phase currents).

Fig. 4.Simulation results for the ECPWM (upper: gating signal for the first phase lag, middle: produced phase voltage, lower: produced phase currents).

Fig. 5.Frequency analysis of the phase voltage produced by the SVPWM.

Fig. 6.Frequency analysis of the phase voltage produced by the ECPWM.

Fig. 7.Frequency analysis of the phase current produced by the SVPWM.

Fig. 8.Frequency analysis of the phase current produced by the ECPWM.

For precise comparison, Table I (Table II) lists the voltage (current) harmonic distortion under different carrier frequencies. The voltage/current harmonics increase when the carrier frequency of the SVPWM is reduced. The ECPWM can reduce the baseband harmonic distortion under a low-carrier frequency setting by applying the error compensation mechanism. Among the three different modulators in Table I/Table II, the harmonic distortion of the ECPWM is the lowest within [0 1 k] Hz. The compensation for the accumulated voltage error enhances the low-frequency performance.

TABLE ISIMULATION RESULT: HARMONIC ANALYSIS OF THE PRODUCED PHASE VOLTAGE

TABLE IISIMULATION RESULT: HARMONIC ANALYSIS OF THE PRODUCED PHASE CURRENT

 

IV. EXPERIMENTS

Two experimental platforms are built to confirm the correctness and the feasibility of the proposed modulator. In the first part of this section, the experimental results for a three-phase VSI connected with a Y-type R–L load are shown. In the second part, a motor drive system using FOC is implemented. Both the SVPWM and the ECPWM are applied and compared. Results indicate that the proposed modulator can be applied directly to the FOC-based motor controller.

A. Experimental Results for VSI Drive

In the first experimental platform, six power MOSFETs (IRF640N) are used to build a three-phase VSI. The DC-link voltage is 15 V, and the output of the VSI is connected to a Y-type R–L load (R = 10 Ω, L = 15 mH). Both the proposed ECPWM and the conventional SVPWM are implemented on a field-programmable gate array (FPGA, EP2C20F484C8, Cyclone II) to produce gating commands.

For the 50 Hz sinusoidal reference with a normalized amplitude of 0.5 and a sampling frequency of 8 kHz, Fig. 9–12 plot the frequency-domain analysis of the measured phase voltage/current. The carrier frequency of the SVPWM (sECPWM) is 8 kHz (4 kHz), and the pulse bit resolution is 10. From Figs. 9–12, the baseband harmonics are reduced by using the proposed ECPWM. Tables III and IV list the harmonic distortions of the phase voltage/current for different carrier frequencies. Similar observations to simulations are obtained as follows: (a) the harmonic distortion increases with the reduction in the carrier frequency by using the SVPWM; (b) using the ECPWM can reduce baseband harmonic distortion under a low-carrier frequency setting.

Fig. 9.Frequency analysis of the phase voltage produced by the SVPWM.

Fig. 10.Frequency analysis of the phase voltage produced by the ECPWM.

Fig. 11.Frequency analysis of the phase current produced by the SVPWM.

Fig. 12.Frequency analysis of the phase current produced by the ECPWM.

TABLE IIIEXPERIMENTAL RESULT: HARMONIC ANALYSIS OF THE PRODUCED PHASE VOLTAGE

TABLE IVEXPERIMENTAL RESULT: HARMONIC ANALYSIS OF THE PRODUCED PHASE CURRENT

B. Experimental Platform for Motor-Speed Controller

To confirm the feasibility of the proposed modulator, the motor drive system using FOC is implemented in a micro-controller (SH7137) to drive a PMSM (HVP75), which is connected to magnetic powder brakes (ZKB010AA). A torque-measuring shaft (DATAFLEXE 22/100) is inserted between the PMSM and the brakes. The input references for the SVPWM and the ECPWM are sampled at a rate of 8 kHz, and the pulse bit resolution for the SVPWM (ECPWM) is 13 (8). The carrier frequency of the SVPWM is 8 kHz, whereas that of the ECPWM is 4 kHz. An FPGA (EP2C35F484C6) is used to receive the desired duty ratio from the micro-controller and generate switching commands to produce the asymmetric switching commands of ECPWM. The block diagram of the motor driver using the SVPWM (ECPWM) is shown in Fig. 13 (Fig. 14). The three-phase power stage is composed of six n-channel power MOSFETs (IRFP360). The specifications are listed in Table V. The dead-time is set to be 2 μs to prevent arm shooting through, and the DC-link voltage is 120 V.

Fig. 13.Block diagram of the implementation platform using the SVPWM.

Fig. 14.Block diagram of the implementation platform using the ECPWM.

TABLE VSPECIFICATIONS OF POWER SWITCH

C. Measured Waveforms for Motor-Speed Control

Fig. 15 shows the switching commands of the upper switch of the first phase lag under a motor speed of 300 rpm. The switching frequency of the ECPWM is half that of the SVPWM. Both modulators can properly produce three-phase current, as shown in Fig. 16. The current ripple produced by the ECPWM is higher than that of the SVPWM because of its lower carrier frequency.

Fig. 15.Switching commands of the SVPWM and the ECPWM.

Fig. 16.Produced three-phase current under a motor speed of 300 rpm.

For precise comparison, the harmonic distortions under different motor speeds are shown in Table VI. Using only half of the switching number, the baseband harmonic distortion of the ECPWM is lower than that of the SVPWM.

TABLE VISWITCHING NUMBER AND CURRENT HARMONIC DISTORTION AT DIFFERENT MOTOR SPEEDS

D. Efficiency of the Motor-Speed Control System

The power supplied to the system (denoted as Pin) and the the efficiency of the motor driving system. The efficiency is then obtained according to η = (Torque×Speed)/Pin×100(%).

The measured motor speed and the output torque under different speed commands are listed in Table VII. The average input/output power within a 15-min operation is listed in Table VIII. The average input power by using the ECPWM is smaller than that by using the SVPWM, whereas the average output power by using the ECPWM is larger than mechanical output power of the motor are measured to obtain that by using the SVPWM under the same motor speed commands. Therefore, the efficiency of the ECPWM is higher than that of the SVPWM. In Table VIII, the efficiency improvement is calculated according to

efficiency improvement = (ηECPWM - ηSVPWM)/ηSVPWM ×100(%).

TABLE VIIPRODUCED MOTOR SPEED AND OUTPUT TORQUE

TABLE VIIIMEASURED INPUT/OUTPUT POWER OF THE MOTOR DRIVE SYSTEM

An average of 7.09% efficiency improvement is obtained by using the ECPWM, and a maximum efficiency improvement of 8.01% is achieved at a motor speed of 400 rpm (refer to Table VIII).

The measured result reveals that the reduction in switching frequency and baseband harmonics helps to improve the efficiency of the motor drive.

E. MOSFET Operating Temperature

The advantage of switching frequency reduction can also be observed from the temperature measurement of MOSFET. Fig. 17 shows the temperature variation in MOSFET during the 15-min operation with a motor speed of 500 rpm. The initial temperature (air temperature in the room) is 25 ℃. After 7.5-min operation, the MOSFET temperature corresponds to the following conditions: the ECPWM rises to 67 ℃, whereas the SVPWM is 94 ℃. Therefore, for the same operating time, the heat dissipation requirement of the ECPWM is lower. The temperature at the end of the operation is 107.4 (80.8) ℃ by using the SVPWM (ECPWM), which shows a great reduction in operation temperature by using the ECPWM. Similar observations are obtained with different motor speeds. The measured temperatures after 15-min operation are listed in Table IX. A maximum reduction of 26.6 ℃ is obtained. Therefore, the proposed method outperforms the SVPWM in reducing the operating temperature.

Fig. 17.Measured temperature within [0 15]-min operating at a speed of 500 rpm.

TABLE IXMEASURED MOSFET TEMPERATURE UNDER VARIOUS MOTOR SPEEDS

A high temperature of power MOSFET leads to low efficiency of the inverter [29]. For every 10 ℃ increase in the working temperature, the lifetime reduction in MOSFET is approximately 40% [26]. Therefore, reducing the temperature of switches not only lessens the heat sink requirement but also improves both the power efficiency and the lifetime of switches.

 

V. CONCLUSION

An ECPWM is proposed in this work. By adjusting the reference signal according to the accumulated error signal, the proposed method can compensate for the difference in the desired and the produced phase voltages. The switching frequency can also be reduced with an improved baseband harmonic performance by selecting the compensating rate as twice the carrier frequency.

In the simulation, a three-phase VSI with R–L load is built. Results imply that the baseband harmonic distortion of the voltage/current produced by the SVPWM increases with decreased carrier frequency. By applying the error compensation mechanism every half-carrier period, the proposed ECPWM improves the baseband harmonic under a low-carrier frequency setting.

In the first experiment, a three-phase VSI with R–L load is built. The measured phase voltages/currents produced by the SVPWM and the ECPWM show similar observations to that obtained in the simulation. A motor drive platform based on FOC is built on Renesas SH7137 to drive a PMSM (HVP75) with magnetic powder brakes to further confirm the effectiveness of the proposed modulator. The measured results indicate that the reduction in both baseband harmonic and carrier frequency can improve the system efficiency.

The advantage of switching number reduction is shown by MOSFET temperature measurement. The measured data imply that the operating temperature is reduced by using the ECPWM with a maximum improvement of 26.6 ℃. Therefore, by using the proposed modulator, the drive system can work with few cooling requirements, high efficiency, and long lifetime of power switches.