• Title/Summary/Keyword: Audio amplifier

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Design of a 94.8dB SNR 1-bit 4th-order high-performance delta-sigma Modulator (94.8dB의 SNR을 갖는 1-bit 4차 고성능 델타-시그마 모듈레이터 설계)

  • Choi, Young-Kil;Roh, Hyung-Dong;Byun, San-Ho;Lee, Hyun-Tae;Kang, Kyoung-Sik;Roh, Jeong-Jin
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.507-508
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    • 2006
  • High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

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Improved 20Mb/s CMOS Optical Receiver for Digital Audio Interfaces (디지털 오디오 인터페이스용 개선된 20Mb/s CMOS 광수신기)

  • Yoo, Jae-Tack;Kim, Gil-Su
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.3 s.357
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    • pp.6-11
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    • 2007
  • This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

A Single-Bit 3rd-Order Feedforward Delta Sigma Modulator Using Class-C Inverters for Low Power Audio Applications (저전력 오디오 응용을 위한 Class-C 인버터 사용 단일 비트 3차 피드포워드 델타 시그마 모듈레이터)

  • Hwang, Jun-Sub;Cheon, Jimin
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.15 no.5
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    • pp.335-342
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    • 2022
  • In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

The Effects of the Auditory Stimulus on Postural Control (자세제어에 대한 청각자극의 효과)

  • Kim, Y.;Jung, J.S.;Kim, N.G.
    • Proceedings of the KOSOMBE Conference
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    • v.1997 no.05
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    • pp.418-421
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    • 1997
  • We examined the effect of the auditory stimulus on postural control. The auditory stimulus control system composed of 8 speakers ,the audio amplifier, the PPI interface and the sound controller. We measured the sway of head position and COP. Our result showed that the auditory stimulus was effective on postural control. It also indicated that the auditory stimulus system might be applied to clinical use as a new postural control training system.

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Novel Current Stress Reduction Technique for Boost Integrated Half-Bridge DC/DC Converter with Voltage Doubler Type Rectifier (전압 체배 정류단을 갖는 부스트 입력형 하프브리지 DC/DC 컨버터를 위한 새로운 전류 스트레스 저감 기법)

  • Park Hong-Sun;Kim Chong-Eun;Moon Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2006.06a
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    • pp.39-42
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    • 2006
  • a current stress reduction technique for a boost integrated half-bridge (BIHB) DC/DC converter with voltage doubler type rectifier is proposed for digital car audio amplifier application. In the proposed circuit, two external capacitors are added parallel to the rectifier diodes in the secondary side of the transformer to shape the primary and the secondary current like rectangular waveforms in every switching instance. The experimental results of a 200W industrial sample show that the peak primary current decreases about by 10A. Thus, the proposed technique shows improved high efficiency.

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Feedback Loudness Control Circuit (피이드백 라우드니스 제어회로)

  • Kim, Ju-Hong;Sim, Gwang-Bo;Eom, Gi-Hwan
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.6
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    • pp.58-61
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    • 1983
  • This is a Loudness Control Circuit in an audio amplifier controlled by feedback type volume control variable resistors. This circuit consists of Bridged Twin T network and a ordinary variable resistor. The variably resistor acts not only as a volume control by varying feedback qupntity, but also as Loudness Control through the characteristics variation by Sound Level. This new Loudness Control Circuit showed ideal compensation characteristics that agree computer simulation and measured datas.

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Control Method and Application of PWM Inverter for Active Silencer (능동소음기를 위한 PWM 인버터의 제어기법 및 적용)

  • Lee, Seung-Yo;Choe, Gyu-Ha;Kang, Jung-Yu;Jang, Do-Hyun
    • Proceedings of the KIEE Conference
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    • 1995.07a
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    • pp.311-314
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    • 1995
  • PWM(Pulse-Width Modulation) is frequently used as control method for inverter. In control of active silencer studied presently, PWM control method can be applied. This paper presents its possibility. As operating source of loudspeaker, inverter is used instead of audio amplifier and PWM controller controls the inverter to make canceling sound. This paper presents that active silencer of inverter-type using the PWM control method makes the canceling sound to acoustic noise and cancels the acoustic noise.

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Design and Construction of a FFT Analyzer Using a Microcomputer (마이크로컴퓨터를 이용한 FFT 분석기의 설계 및 제작)

  • Lee, Hyeun Tae;Kim, Jung Gyu;Lee, Sang Bae
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.944-949
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    • 1986
  • By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

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Design of a CMOS Single Bit 3rd Order Delta-Sigma Modulator with Switched Operational Amplifier (스위치드 연산증폭기를 이용한 CMOS 단일비트 3차 델타시그마 변조기 설계)

  • Lee, Han-Ul;Dai, Shi;Yoo, Tai-Kyung;Lee, Keon;Yoon, Kwang-Sub;Lee, Sang-Min
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.8A
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    • pp.712-719
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    • 2012
  • This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

Design of the New Third-Order Cascaded Sigma-Delta Modulator for Switched-Capacitor Application (스위치형 커패시터를 적용한 새로운 형태의 3차 직렬 접속형 시그마-델타 변조기의 설계)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.906-909
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    • 2006
  • This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

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