• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.887-890
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• 1998

We present a method for initialization of asynchronous circuits using binary decision space representation. From state transition graph(STG) which is given as a specification a circuit, the BDD is generated to solve the state space explosion problem which is caused by concurrecy of STG. We first step, we construct the necessary informaton as a form of K-map from BDD, then find an initial state on the K-map by assignment of don't care assignment.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1597-1604
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• 2005

Recursive Patching is an efficient multicast technique for large-scale video on demand systems and recursively shares existing video streams with asynchronous clients. When Recursive Patching initiates a transition stream, it always makes a transition stream have additional data for the worst future request. In order to share a VOD server's limited network bandwidth efficiently, this paper proposes Practical Patching that removes the unnecessary data included in the transition stream. The proposed Practical Patching dynamically expands ongoing transition streams when a new request actually arrives at the server. As a result, the transition streams never have unnecessary data. Simulation result confirmed that the proposed technique is better than Recursive Patching in terms of service latency and defection rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.139-147
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• 2014

We address the problem of corrective control for two asynchronous sequential machines in parallel connection. Each asynchronous machine receives the same external input and shows independent state transition characteristics. We propose a novel control scheme in which only one corrective controller is employed so as to make the closed-loop system of each machine match the behavior of the corresponding reference model. Compared with the former method utilizing two corrective controllers, our scheme can reduce the controller size and computational load in controller design. We present the existence condition and design procedure for a state-feedback corrective controller under the assumption that the controlled machines are of input/state type. The design procedure for the proposed controller is described in an illustrative example.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.237-239
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• 1983

본 논문은 어떤 비동기적인 제어계가 상태 천이도(transition diagram)로 표현되기만 하면 이 입력으로부터 직접 비동기 순차회로를 구성 할 수 있는 알고리즘을 제시하고 있다. 이로써 비동기 회로를 쉽게 하드웨어로 실현 할수 있도록 하였다.