• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5361-5374
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• 2016

Combining channel coding and network coding in a physical layer in a fading channel, generalized joint channel-network coding (G-JCNC) is proved to highly perform in a two-way relay channel (TWRC). However, most relevant discussions are restricted to symmetric networks. This paper investigates the G-JCNC protocols in an asymmetric TWRC (A-TWRC). A newly designed encoder used by source nodes that is dedicated to correlate codewords with different orders is presented. Moreover, the capability of a simple common non-binary decoder at a relay node is verified. The effects of a power match under various numbers of iteration and code lengths are also analyzed. The simulation results give the optimum power match ratio and demonstrate that the designed scheme based on G-JCNC in an A-TWRC has excellent bit error rate performance under an appropriate power match ratio.

• Journal of Power Electronics
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• v.11 no.6
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.155-156
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• 2015

This paper proposes a high efficiency wireless power transfer system with an asymmetric 4-coil resonator. It presents a theoretical analysis, an optimal design method, and experimental results. In the proposed asymmetric 4-coil system, the primary side consists of a source coil and two transmitter coils which are called intermediate coils, and in the secondary side, a load coil serves as a receiver coil. In the primary side, two intermediate coils boost the apparent coupling coefficient at around the operating frequency. Because of this double boosting effect, the system with an asymmetric 4-coil resonator has a higher efficiency than the conventional symmetric 4-coil system. The prototype operates at 90 kHz ofswitching frequency and has 200 mm of the power transmission distance between the primary side and the secondary side. An AC-DC overall system efficiency of 96.56% has been achieved at 3.3 kW of output power.

• Journal of computational fluids engineering
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• v.11 no.3 s.34
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• pp.22-27
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• 2006

Flow around a guided missile in high maneuver, i.e. at a high angle of attack, shows complex phenomena. It is well known that even in geometrically symmetric conditions the flow around a missile at high angles of attack can generate unexpected large side forces and yaw moments due to asymmetric vortices. In this paper, a CFD code (FLUENT) based on the Navier-Stokes equations was used for the numerical analysis to find a suitable numerical mechanism for generation of asymmetric vortices. It is shown that a numerical technique of applying different surface roughness to a specific area of the missile nose surface gives the best fit in comparison with the experimental results. In addition, a numerical investigation of variations of side forces and pressure distributions with angle of attack and roll angle was conducted for the purpose of identifying the source of vortex asymmetries.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.7
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• pp.747-749
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• 2016

We consider a time-division multiple-access relay channel (MARC), in which two source nodes (SNs) transmit data with different data rate to a destination node (DN) with the help of a relay node (RN) using network coding (NC). However, due to its asymmetric data rate, the RN cannot combine the received bits by XOR NC. In this paper, we compare with the problem of asymmetric data rates by using zero padding and hierarchical 16QAM.

• Journal of Power Electronics
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• v.18 no.2
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• pp.343-355
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• 2018

A wide-voltage-conversion range bidirectional DC-DC converter is proposed in this paper. The topology is comprised of one typical LC energy storage component and a special common grounded asymmetric H-bridge with four active power switches/anti-parallel diodes. The narrow output PWM voltage is generated from the voltage difference between two normal (wider) output PWM voltages from the asymmetric H-bridge with duty cycles close to 0.5. The equivalent switching frequency of the output PWM voltage is double the actual switching frequency, and a wide step-down/step-up ratio range is achieved. A 300W prototype has been constructed to validate the feasibility and effectiveness of the proposed bidirectional converter between the variable low voltage side (24V~48V) and the constant high voltage side (200V). The slave active power switches allow ZVS turn-on and turn-off without requiring any extra hardware. The maximum conversion efficiency is 94.7% in the step-down mode and 93.5% in the step-up mode. Therefore, the proposed bidirectional topology with a common ground is suitable for energy storage systems such as renewable power generation systems and electric vehicles with a hybrid energy source.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.793-798
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• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.989-991
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• 2001

The new converter topology using full bridge inverter for the switched reluctance motor drives is proposed. The proposed SRM drives are supplied by the pulse voltage source, while the conventional drives are supplied by dc voltage source. Proposed converter maintains the characteristics of asymmetric bridge converter and has advanced characteristics.