• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• 전력전자학회논문지
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• 제17권4호
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• pp.306-314
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• 2012

In case of the conventional DC-AC inverter using two DC-DC converters with unipolar output capacitor voltages, for generating the AC output voltage, the output capacitor voltages of its each DC-DC converter must be higher than the DC input voltage. To solve this problem, this paper proposes a single-phase DC-AC inverter using two embedded Z-source converters with bipolar output capacitor voltages. The proposed inverter is composed of two embedded Z-source converters with common DC source and output AC load. The AC output voltage is obtained by the difference of the output capacitor voltages of each converter. Though the output capacitor voltage of converter is relatively low compared to the conventional method, it can be obtained the same AC output voltage. Moreover, by controlling asymmetrically the output capacitor voltage, the AC output voltage of the proposed system is higher than the DC input voltage. To verify the validity of the proposed system, a DSP(TMS320F28335) based single-phase embedded Z-source DC-AC inverter was made and the PSIM simulation was performed under the condition of the DC source 38V. As controlled symmetrically and asymmetrically the output capacitor voltages of each converter, the proposed inverter could produce the AC output voltage with sinusoidal waveform. Particularly, in case of asymmetric control, a higher AC output voltage was obtained. Finally, the efficiency of the proposed system was measured as 95% and 97% respectively in case of symmetric and asymmetric control.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.533-536
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• 1998

The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by $0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties.

• ETRI Journal
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• 제37권4호
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• pp.717-726
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• 2015

In this paper, we study an asymmetric two-way relaying network where two source nodes intend to exchange information with the help of multiple relay nodes. A hybrid time-division broadcast relaying scheme with joint relay selection (RS) and power allocation (PA) is proposed to realize energy-efficient transmission. Our scheme is based on the asymmetric level of the two source nodes' target signal-to-noise ratio indexes to minimize the total power consumed by the relay nodes. An optimization model with joint RS and PA is studied here to guarantee hybrid relaying transmissions. Next, with the aid of our proposed intelligent optimization algorithm, which combines a genetic algorithm and a simulated annealing algorithm, the formulated optimization model can be effectively solved. Theoretical analyses and numerical results verify that our proposed hybrid relaying scheme can substantially reduce the total power consumption of relays under a traffic asymmetric scenario; meanwhile, the proposed intelligent optimization algorithm can eventually converge to a better solution.

• International Journal of Control, Automation, and Systems
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• 제6권6호
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• pp.809-817
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• 2008

Program plagiarism is widespread due to intelligent software and the global Internet environment. Consequently the detection of plagiarized source code and software is becoming important especially in academic field. Though numerous studies have been reported for detecting plagiarized pairs of codes, we cannot find any profound work on understanding the underlying mechanisms of plagiarism. In this paper, we study the evolutionary process of source codes regarding that the plagiarism procedure can be considered as evolutionary steps of source codes. The final goal of our paper is to reconstruct a tree depicting the evolution process in the source code. To this end, we extend the well-known bioinformatics approach, a local alignment approach, to detect a region of similar code with an adaptive scoring matrix. The asymmetric code similarity based on the local alignment can be considered as one of the main contribution of this paper. The phylogenetic tree or evolution tree of source codes can be reconstructed using this asymmetric measure. To show the effectiveness and efficiency of the phylogeny construction algorithm, we conducted experiments with more than 100 real source codes which were obtained from East-Asia ICPC(International Collegiate Programming Contest). Our experiments showed that the proposed algorithm is quite successful in reconstructing the evolutionary direction, which enables us to identify plagiarized codes more accurately and reliably. Also, the phylogeny construction algorithm is successfully implemented on top of the plagiarism detection system of an automatic program evaluation system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.576-580
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• 2013

We investigate the enhanced effects of asymmetry ratio variations of the source and drain area in silicon (Si) field-effect transistor (FET). Photoresponse according to the variation of asymmetry difference between the width of source and drain are obtained by using the plasmonic terahertz (THz) wave detector simulation based on technology computer-aided design (TCAD) with the quasi-plasma 2DEG model. The simulation results demonstrate the potential of Si FETs with asymmetric source and drain structures as the promising plasmonic THz detectors.

• ETRI Journal
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• 제24권5호
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• pp.341-348
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• 2002

We propose an asymmetric sampled grating laser and a multi-wavelength laser array associated with it. Asymmetric sampling periods combined with an index shifter make it possible to use first order reflection for lasing operations. With the structure of our design, we achieved a simple fabrication procedure as well as a high yield without using complex and time-consuming e-beam lithography for multi-period gratings. We analyzed the effect of mirror coating by numerical analysis to improve single mode and power extraction performance. By using high reflection-antireflection coatings, we obtained high power extraction efficiency without degradation of the single mode property. For the multi-wavelength laser array, to gain wavelength control, we varied the sampling periods from one laser to an adjacent laser across the array. With this approach, we showed the feasibility of an array of up to 30 channels with 100 GHz wavelength spacing.

• 한국컴퓨터산업학회논문지
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• 제2권9호
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• pp.1209-1218
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• 2001

본 논문은 이동 Ad Hoc 망 라우팅 프로토콜 중, 비대칭 경로를 지원하는 동적 소스 라우팅 프로토콜에 관한 연구이다. 기존의 동적 소스 라우팅 프로토콜은 양방향 경로만을 사용하도록 구현되어있다. 그러나 실제적인 무선환경에서는 단말의 비대칭성이나 무선환경 특성 등에 기인한 단방향 링크가 존재할 수 있다. 따라서 본 논문에서는 좀 더 일반적인 무선환경에 맞는 이동 Ad Hoc 망 라우팅 프로토콜을 구현하기 위하여 비대칭 경로를 지원하도록 하였다. 특히 이동성으로 인한 경로 실패를 인식한 경우, 신속한 경로 재설정을 수행하기 위해 개선된 다중경로유지 기법을 사용하였다.

• Nuclear Engineering and Technology
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• 제52권11호
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• pp.2601-2606
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• 2020

In this study, we expanded the performance of the existing EXVol code and performed empirical experiments and calculations. A high-resolution gamma spectroscopy system was constructed, and a standard point source and a standard volume source were measured with an HPGe detector with 43.1% relative efficiency. EXVol was verified by quantitative comparison of the detection efficiencies determined by measurements and calculations. To introduce the concept of the detector scanning that occurs in the actual measurement into the EXVol code, a collimator was placed between the source and detector. The detection efficiency was determined in the asymmetric arrangement of the source and detector with a collimator. A collimator made of lead with a diameter of 15 mm and a thickness of 50 mm was installed between the source and the detector to determine the detection efficiency at a specific location. The calculation result was contour plotted so that the distribution of detection efficiency could be visually confirmed. The relative deviation between the measurements and calculations for the coaxial and asymmetric structures was 10%, and that for the collimation structure was 20%. The results of this study can be applied to research using γ-ray measurements.

• 대한전자공학회논문지SD
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• 제38권7호
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• pp.464-472
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• 2001

집적도 향상을 위해 사용되는 비대칭 n-MOSFET를 0.35 ㎛ CMOS공정으로 제조하여 그 전기적 특성을 조사고 전기적 모델을 제시하였다. 비대칭형 n-MOSFET는 대칭형 n-MOSFET에 비해 포화영역의 드레인 전류는 감소하였으며, 선형영역의 저항은 증가하였다. 그리고 비대칭형 n-MOSFET에서 보다 낮은 기판 전류가 측정되었다. 측정결과를 찬조하여 비대칭 n-MOSFET를 회로설계에 용이하게 사용할 수 있도록 기존의 대칭형 소자 모델을 개선한 새로운 모델을 제시하였다. 이 모델링의 정확성을 MEDICI 시뮬레이션을 통해 확인하였고, 대부분의 게이트 폭 범위에서 계산된 비대칭 n-MOSFET의 포화 전류 값은 측정값과 거의 일치하였다.