• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.285-289
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• 2002

In this paper, microstrip line-probe feeding patch array antenna with center frequency 5.8㎓ is designed and manufactured. The microstrip line - probe feeding structure has broadband characteristic and be able to modify the array structure for improving antenna gain. In this result, microstrip line-probe feeding patch array antenna has 17.6% bandwidth and 8㏈i antenna gain, respectively.

• ETRI Journal
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• v.27 no.6
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• pp.677-684
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• 2005

A phased array antenna was fabricated using four-element ferroelectric phase shifters with a coplanar waveguide (CPW) transmission line structure based on a $Ba_{0.6}Sr_{0.4}TiO_3(BST)/MgO$ structure. Epitaxial BST films were deposited on MgO (001) substrates by pulsed laser deposition. To attain the large differential phase shift and small losses for a ferroelectric CPW phase shifter, an impedance-matching-part adding technique between the effective transmission line and connecting cable was used. The return loss and insertion loss for this techniqueadapted BST CPW device were improved with respect to those for a normal BST CPW device. For an X-band phased array antenna system consisting of ferroelectric BST CPW phase shifters, power divider, dc block, patch antenna, and programmed dc power, the steering beam could be tilted by $15^{\circ}$ in either direction.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1993.10a
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• pp.81-90
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• 1993

The optimum design of a structure requires the determination of the economical member size and shape of the structure which satisfies the design condition and function. In this study, the process of design automatization of three-dimensional truss structure introduces the optimization technique tests its application in the design automatization, proposes its application method and applies the example structure of the parabolic antenna truss. Using the Formex Algebra of configuration function, the structure's mesh-generation is automatized. By using the program developed in this study, the input member array, member size and load condition designer can generate the input data file for the structure analysis and optimum design. This study is aimed at the development of a design automatization system that search for tile optimum value of a structure design by observing the structure's sensitivity from the modification of member array and member property.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.347-356
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• 1996

In this paper, we present the circular array structure for estimating the temporal and spatial specturm of multiple narrowband incoherent signals which have different frequencies. The conventional linear array is computationally demanding for simultaneously estimating the spatial and temporal spectrum since it requires the tapped delay line filer. The statistical performance of the circular array is never deteriorated eve though it requires much less computational load than the uniform linear array. Especially, it is shown that the circular array resolves the direction-of-arrivals of the multiple signals without the spatial and temporal aliasing the fundamental nonuniform-sampling property prossessed by it. Computer simulation results are shown to demonstrate the better performance achieved with the circular array geometry relative to that obtained with a uniform linear array with taps.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.2
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• pp.61-70
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• 1984

This paper examines the array antenna theory, basic relations between the array size (aperture) and its beamwidth and resultant patterns. This paper also provides array antenna system design criteria, mainly maximizing the signal-to-noise ratio (SNR) and its corresponding optimum array structure and weight functions. Explicit new expressions for array performance are also illustrated in terms of the array output SNR. An example is provided for a 37-element planar array to explicitly illustrate the beam-forming and nulling operations of the array. Fundamentals of sidelobe canceller (SLC) systems have been discussed along with a derivation of new SLC equations for optimum weights.

• Korean Journal of Materials Research
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• v.11 no.11
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• pp.929-935
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• 2001

Two-dimensional computer simulations were conducted on percolation structure in which second phases of various aspect ratios were arranged in a lattice (matrix). The second phases were randomly arranged in an array with two different computational programs; one prohibiting an overlap among second phases and the other allowing the overlap. From the simulation prohibiting the overlap, it was predicted that a complete path was formed at less amounts of the second phase with higher aspect ratios. In the simulation allowing the overlap, a complete path throughout the array was formed by arranging the second phase of an aspect ratio of 1. 5, 20, 100 with less than 59%, 43%, 19%, 4% in the array, respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.59-63
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• 2000

For the Mo-tip field emitter array, the method by which the geometrical structure of the gate insulator wall could be modified in order to improve field emission properties(turn-on voltage and gate leakage current). The device having a gate insulator of complex shape, which means the combined geometrical structure with round shape made by wet etching and vertical shape made by dry etching processes, was fabricated and the field emission properties of the three kinds of devices were compared. As a result, the electric field applied to tip apex could be increased and gate leakage current could be decreased by employing the gate insulator having geometrical wall structure of mixed shape. Finally, the obtained empirical results were analyzed by simulation of electric field distribution at/near the tip apex and gate insulator using SNU-FEAT simulator.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.211-214
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• 2000

In this paper, a discrete-time S-dimensional chaos circuit (S = 1,2,3,4,...) with array structure is proposed. By employing array structure which consists of 1-dimensional chaos circuits, the proposed circuit can achieve long working-life. This feature is favorable to exploit as a building block of chaos application systems to get into home electric appliances. Further more, the proposed circuit synthesized using switched-current (SI) techniques is suitable for integration. Concerning the proposed circuit, SPICE simulations are performed. SPICE simulations showed that the proposed circuit can generate the chaotic signals in spite of the fault of the building blocks of the proposed circuit. The proposed circuit is integrable by a standard BiCMOS technology.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.8
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• pp.1461-1465
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• 2007

A micromachined sensor part for an infrared focal plane array has been designed and fabricated. Amorphous silicon was adapted as a sensing material, and silicon nitride was used as a membrane material. To get a good efficiency of infrared absorption, the sensor was made as a ${\lambda}/4$ cavity structure. All the processes were done in $0.5\;{\mu}m$ iMEMS fab. in the Electronics and Telecommunication Research Institute (ETRI). The processed MEMS sensor structure had a small membrane deflection less than $0.3\;{\mu}m$. This excellent deflection property can be attributed to the rigorous balancing of the stresses of individual layers. The efficiency of infrared absorption was more than 75% in the wavelength range $8\;-\;14\;{\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.