• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12B
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• pp.1083-1096
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• 2008

This paper proposes an energy-aware path management scheme, so-called the TBP(Threshold based Back-Pressure) algorithm, which is designed for lifetime extension of the energy-constrained wireless sensor networks. With the goal of fair energy consumptions, we extensively utilize the available paths between the source and the sink nodes. The traffic distribution feature of the TBP algorithm operates in two scales; the local and the whole routing area. The threshold and the back-pressure signal are introduced for implementing those operations. It is noticeable that the TBP algorithm maintains the scalability by defining both the threshold and the back-pressure signal to have their meanings locally confined to one hop only. Throughout several experiments, we observe that the TBP algorithm enhances the network-wide energy distribution. which implies the extension of the network lifetime. Additionally, both the delay and the throughput outcomes show remarkable improvements. This shows that the energy-aware path control scheme holds the effects of the congestion control.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.2
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• pp.113-119
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• 2017

In this paper, we have shown the performance analysis results of the LoRa low power wide area network under duty cycle local regulation in Korean RFID/USN frequency band. Especially, we analyzed uplink throughput and data transmission time of a single LoRa end device. From the analysis results, duty cycle regulation, in which a data transmission should be ended within 0.4 second, limits the performance of LoRa network. Therefore, it is necessary to revise Korea's duty cycle regulation referencing EU regulation in order to assess LoRa network in Korea.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.526-534
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• 2014

In this paper, for the WiMedia Distributed Medium Access Control (D-MAC) protocol based on UWB. performance degradation due to the Distributed Reservation Protocol (DRP) conflict problem caused by devices' mobility is analyzed. And a DRP relay protocol and a DRP conflict resolution (CR) are proposed to overcome the performance degradation at DRP conflicts. In order to give the loser device at DRP conflicts a chance to maintain resources, the proposed DRP relay protocol executed at each device helps the loser device reserve an indirect link maintaining the required resources via a relay node. Simulation results considering the mobile environment have indicated that the DRP relay combined with the CR prevent the throughput decrease even though mobility of devices increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.308-316
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• 2015

In this paper, we carried out performance comparison of four routing protocols that had been proposed for mobile ad hoc networks using the NS-3 network simulator. Those four routing protocols consist of two proactive routing protocols, DSDV(destination-sequenced distance vector) and OLSR(optimized link state routing), and two reactive routing protocols, AODV(ad-hoc on-demand distance vector) and DSR(dynamic source routing). Two performance metrics, system throughput and packet delivery ratio, are adopted and performance evaluation was carried out in a square communication area where each communicating mobile node moves independently. Numerical results show that the AODV routing protocol provides the best performance among those four routing protocols.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1332-1340
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• 2007

This paper describes an efficient hardware design of key wrap/unwrap algorithm for security layer of WiBro system. The key wrap/unwrap core (WB_KeyWuW) is based on AES (Advanced Encryption Standard) algorithm, and performs encryption/decryption of 128bit TEK (Traffic Encryption Key) with 128bit KEK (Key Encryption Key). In order to achieve m area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented by using field transformation technique. As a result, the gate count of the WB_KeyWuW core is reduced by about 25% compared with conventional LUT (Lookup Table)-based design. The WB_KeyWuW con designed in Verilog-HDL has about 14,300 gates, and the estimated throughput is about $16{\sim}22-Mbps$ at 100-MHz@3.3V, thus the designed core can be used as an IP for the hardware design of WiBro security system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.