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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Cortex-M0 based Security System-on-Chip Embedded with Block Ciphers and Hash Function IP

블록암호와 해시 함수 IP가 내장된 Cortex-M0 기반의 보안 시스템 온 칩

  • Choe, Jun-Yeong (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Choi, Jun-Baek (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2019.06.16
  • Accepted : 2019.06.17
  • Published : 2019.06.30
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Abstract

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.

블록암호 알고리듬 ARIA와 AES 그리고 해시 함수 Whirlpool을 단일 하드웨어로 통합 구현한 AAW(ARIA- AES-Whirlpool) 크립토 코어를 Cortex-M0 CPU에 슬레이브로 인터페이스한 보안 SoC(System-on-Chip) 설계에 대해 기술한다. AAW 크립토 코어는 ARIA, AES, Whirlpool의 알고리듬 특성을 이용한 하드웨어 공유를 통해 저면적으로 구현되었으며, 128-비트와 256-비트의 키 길이를 지원한다. 설계된 보안 SoC 프로토타입을 FPGA 디바이스에 구현하고, 하드웨어-소프트웨어 통합 검증을 하였다. AAW 크립토 코어는 5,911 슬라이스로 구현이 되었으며, AAW 크립토 코어가 포함된 AHB_Slave는 6,366 슬라이스로 구현되었다. AHB_Slave의 최대 동작 주파수는 36 MHz로 예측되었으며, ARIA-128, AES-128의 데이터 처리율은 각각 83 Mbps, 78 Mbps이고, Whirlpool 해시 함수의 512-비트 블록의 처리율은 156 Mbps로 평가되었다.

Keywords

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Fig. 1. Architecture of the Cortex-M0 based SoC. 그림 1. Cortex-M0 기반의 SoC 구조

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Fig. 2. AAW_Slave module. 그림 2. AAW_Slave 모듈

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Fig. 3. AHB_SCntl block. 그림 3. AHB_SCntl 블록

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Fig. 4. Architecture of AAW core. 그림 4. AAW 코어의 구조

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Fig. 5. BFM simulation results of AAW_Slave, (a) encryption mode of ARIA-128, (b) encryption mode of AES-256, (c) Whirlpool hash mode. 그림 5. AAW_Slave의 BFM 시뮬레이션 결과 (a) ARIA-128의 암호화 모드, (b) AES-256의 암호화 모드, (c) Whirlpool hash 모드

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Fig. 6. FPGA verification setup 그림 6. FPGA 검증 시스템 구성

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Fig. 7. FPGA verification results of the security SoC (a) Whirlpool hash mode (b) ARIA-128 mode 그림 7. 설계된 보안 SoC의 FPGA 검증 결과 (a) Whirlpool hash 모드 (b) ARIA-128 모드

Table 1. Control register setting for operation modes. 표 1. 동작 모드를 위한 컨트롤 레지스터 설정

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Table 2. Performance of the AHB_Slave. 표 2. AHB_Slave의 성능

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References

  1. Ali Ismail Awad, "Introduction to information security foundations and applications," In book: Information Security: Foundations, Technologies and Applications. Chapter: 1, The Institution of Engineering and Technology (IET), Editors: Ali Ismail Awad and Michael Fairhurst, 2018.
  2. Neowine developed security SoC DORCA -3 supporting asymmetric-key encryption, https://news.v.daum.net/v/20180109133504243.
  3. MS500: Low Power, Advanced Security Features for IoT, http://kr.ewbm.com/page/sub2_1
  4. P. Choi, Design and Implementation of High-Performance and Low-Complexity Security System on Chip (SoC), Ph. D. Dissertation, Hanyang University, 2017.
  5. A. P. Deb Nath, S. Ray, A. Basak and S. Bhunia, "System-on-chip security architecture and CAD framework for hardware patch," 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju, pp.733-738, 2018. DOI: 10.1109/ASPDAC.2018.8297409
  6. KS X 1213:2004, 128 bit Block Encryption Algorithm ARIA, Korean Agency for Technology and Standards (KATS), 2004.
  7. FIPS-197, Advanced Encryption Standard, National Institute of Standard and Technology (NIST), 2001.
  8. Paulo S. L. M. Barreto and Vincent Rijmen, "The WHIRLPOOL Hashing Function," pp.1-20, 2003. DOI: 10.1.1.529.3184
  9. ARM Cortex-M0, https://developer.arm.com/products/processors/cortex-m/
  10. K. B. Kim and K. W. Shin, "An Integrated Cryptographic Processor Supporting ARIA/AES Block Ciphers and Whirlpool Hash Function," Journal of Institute of Korean Electrical and Electronics Engineers, vol. 22, no. 1, pp. 38-45, 2018. DOI: 10.7471/ikeee.2018.22.1.38