• Title/Summary/Keyword: Area Throughput

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Study on the correlation between the soil bacterial community and growth characteristics of wild-simulated ginseng(Panax ginseng C.A. Meyer) (토양세균군집과 산양삼 생육특성 간의 상관관계 연구)

  • Kim, Kiyoon;Um, Yurry;Jeong, Dae Hui;Kim, Hyun-Jun;Kim, Mahn Jo;Jeon, Kwon Seok
    • Korean Journal of Environmental Biology
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    • v.37 no.3
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    • pp.380-388
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    • 2019
  • The studies regarding soil bacterial community and correlation analysis of wild-simulated ginseng cultivation area are insufficient. The purpose of this study was to investigate the correlation between soil bacterial community and growth characteristics of wild-simulated ginseng for selection of suitable cultivation area. The bacterial community was investigated by high throughput sequencing technique (Illumina platform). The correlation coefficient between soil bacterial community and growth characteristics were analyzed using Spearman's rank correlation. The soil bacterial community from soil samples of 8 different wild-simulated ginseng cultivated area exhibited two distinct clusters, cluster 1 and cluster 2. The relative abundance of Proteobacteria (35.4%) and Alphaproteobacteria(24.4%) was observed to be highest in all soil samples. The lower soil pH and higher abundance of Acidobacteria resulted in increased growth of wild-simulated ginseng. Additionally, abundance of Acidobacteriia (class) and Koribacteraceae (family) demonstrated significant positive correlation with fresh weight of wild-simulated ginseng. The results of this study clearly state the correlation between growth characteristic and soil bacterial community of wild-simulated ginseng cultivation area, thereby offering effective insight into selection of suitable cultivation area of wild-simulated ginseng.

Evaluation of the Implementation of ISO 11783 for 250 kbps Transmission Rate of Tractor Electronic Control Unit

  • Lee, Dong-Hoon;Lee, Kyou-Seung;Moon, Jae-Min;Park, Seung-Je;Kim, Cheol-Soo;Kim, Myeong-Ho;Cho, Yong-Jin;Kim, Seong-Min
    • Journal of Biosystems Engineering
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    • v.37 no.4
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    • pp.225-232
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    • 2012
  • Purpose: Accurate monitoring of information from various agricultural vehicles is one of the most important factors for appropriate management strategy of field operations. While there has been a number of study and design on applications of sensors and actuators for data acquisition and control system in tractor, incompatibility between various customized hardware and software has become a major obstacle to the universal deployment in real field operation. International standard for implementation of electronic control unit (ECU) in agricultural vehicles has becoming a mandatory requirement for inter-operation compatibility in the international trade of agricultural vehicle industries. The ISO 11783 standard is basically based upon well known communication technology designated using the controller area network (CAN) bus. While CAN bus could provide 1.0 Mbps of communication speed, the standard only recommended 250 kbps. Methods: This study presents the implementation and evaluation of ISO 11783 for tractor electronic control units (TECU)with a higher transmission rate from multiple ECU than 250 kbps. Throughput and loss rate of the developed prototype were calculated across manipulated bus load for laboratory experimental tests, and the maximum requirement of transmission rate by ISO 11873 was satisfied with lower than 60% of bus load. Results: Field tests with a TECU implemented to process messages from global positioning system (GPS) receiver resulted that the root mean square error of position information was lower than 4 m with 0.5 m/s as a travelling speed. Conclusions: Results of this study represent the utilization of the international standard ISO 11783 to providepractical developments in terms with the inter-operability of TECU.

An Area-Efficient Design of Merged TEA Block Cipher for Mobile Security (모바일 보안용 병합 TEA 블록 암호의 면적 효율적인 설계)

  • Sonh, Seungil;Kang, Min-Goo
    • Journal of Internet Computing and Services
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    • v.21 no.3
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    • pp.11-19
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    • 2020
  • In this paper, a merged TEA block cipher processor which unifies Tiny Encryption Algorithm(TEA), extended Tiny Encryption Algorithm(XTEA) and corrected block TEA(XXTEA) is designed. After TEA cipher algorithm was first designed, XTEA and XXTEA cipher algorithms were designed to correct security weakness. Three types of cipher algorithm uses a 128-bit master key. The designed cipher processor can encrypt or decrypt 64-bit message block for TEA/XTEA and variable-length message blocks up to 256-bit for XXTEA. The maximum throughput for 64-bit message blocks is 137Mbps and that of 256-bit message blocks is 369Mbps. The merged TEA block cipher designed in this paper has a 16% gain on the area side compared to a lightweight LEA cipher. The cryptographic IP of this paper is applicable in security module of the mobile areas such as smart card, internet banking, and e-commerce.

An efficient hardware implementation of 64-bit block cipher algorithm HIGHT (64비트 블록암호 알고리듬 HIGHT의 효율적인 하드웨어 구현)

  • Park, Hae-Won;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.1993-1999
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    • 2011
  • This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

A Distributed Medium Access Control Protocol Based on Adaptive Collision Detection in Dense Wireless Local Area Networks (밀집 무선랜 환경에서 적응적 충돌 검출 기반의 분산 매체접속제어 프로토콜)

  • Choi, Hyun-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.12
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    • pp.2259-2266
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    • 2016
  • Recently dense wireless local area networks (WLANs) emerge as the number of WLAN cells and stations increases. In such dense WLAN environment, this paper proposes a new distributed medium access control (MAC) protocol. The proposed MAC protocol extends the previous CSMA with collision resolution (CSMA/CR) that uses a single collision detection (CD) phase and employs multiple CD phases to resolve more collisions. It checks the collision detection in each CD phase and stops the CD phase if consecutive non-detected CD phases occur more than the threshold. Therefore, the proposed protocol can control the number of CD phases adaptively according to the number of accessing stations and increase the probability of collision resolution while decreasing the packet overhead. The simulation results show that the proposed adaptive CSMA/CR protocol employs a variable number of CD phases according to the number of stations and achieves a greater throughput than the previous CSMA/CR protocol using the fixed number of CD phases.

Random Channel Allocation Scheme Based on Split Algorithm in HIPERLAN 2 (HIPERLAN Type 2에서 Split 알고리즘에 기반한 랜덤채널 할당 기법)

  • 황의석;고유창;이승규;윤철식;이형우;조충호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.9A
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    • pp.717-727
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    • 2003
  • The HIPERLAN/2(HIgh PERformance Local Area Network Type2) is one of the wireless LAN standards for providing raw data rates of up to 54 Mbps. The MAC protocol of HIPERLAN/2 is based on TDMA/TDD, and resources in one MAC frame can be allocated dynamically by Access Point(AP). The random channel(RCH) is defined for the purpose of giving a mobile terminal the opportunity to request transmission resources in the uplink MAC frames. It is desirable that the number of RCHs is dynamically adapted by the AP depending on the current traffic situation. Allocation of excessive RCHs may waste radio resources and insufficient RCHs compared to traffic loads may result in many collisions in access attempts. We propose an RCH allocation scheme based on split algorithm in HIPERLAN/2. The simulation and analytic results show that the proposed scheme achieves a higher channel throughput, lower access delay and delay jitter than previously proposed RCH allocation schemes.

Acceleration of FFT on a SIMD Processor (SIMD 구조를 갖는 프로세서에서 FFT 연산 가속화)

  • Lee, Juyeong;Hong, Yong-Guen;Lee, Hyunseok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.2
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    • pp.97-105
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    • 2015
  • This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

A design of compact and high-performance AES processor using composite field based S-Box and hardware sharing (합성체 기반의 S-Box와 하드웨어 공유를 이용한 저면적/고성능 AES 프로세서 설계)

  • Yang, Hyun-Chang;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.67-74
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    • 2008
  • A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

Contention-Free Access Protocol Based Energy-Efficient Transmission for Wireless PANs (비경쟁 접근 프로토콜 기반 WPAN을 위한 에너지 효율적인 전송기법)

  • Joo, Yang-Ick;Lee, Yeon-Woo;Jung, Min-A;Choi, Myeong-Soo;Kim, Seo-Gyun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.4A
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    • pp.450-457
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    • 2008
  • One of very essential techniques for enlarging lifetime of energy-constrained wireless personal area network (WPAN) devices is energy-efficient transmission technique. If the WPAN is operated based on a TDMA protocol, the satisfaction of QoS requirements at each allocated time slot is another important factor to be considered. We therefore propose an energy-efficient transmission scheme for WPANs operating with a contention-free medium access protocol such as TDMA, as well as satisfying QoS requirement. The proposed algorithm determines the optimum combination of transmit power, physical data rate and fragment size required to simultaneously minimize the energy consumption and satisfy the required QoS in each assigned time duration, considering all the possible energy-minimization related parameters. The proposed algorithm demonstrated the improved performance results in terms of throughput and energy consumption via computer simulation.

A Deterministic Access Protocol in WiMedia Wireless Personal Area Networks (WiMedia 초고속 근거리 무선 통신에서의 결정적 접근 프로토콜)

  • Park, Hyun-Hee;Pack, Sang-Heon;Kim, Yong-Sun;Kang, Chul-Hee
    • Journal of IKEEE
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    • v.13 no.3
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    • pp.7-17
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    • 2009
  • WiMedia UWB technology is a fully distributed data communication technology developed for the application demanding a high data transmission rate in the wireless PAN area. In general, devices can send data either by reserving time slots or by using prioritized CSMA/CA. If the PCA protocol of prioritized CSMA/CA is used, they are suffered congestion as the number of devices increases. In this paper, we propose a Deterministic Access Protocol(DAP) in WiMedia WPANs. A DAP is a method to transmit data in the non-reserved DRP period without competition as each device informs the beacon order information in the beacon period and the queue information. In addition, the problem that the devices with a lower beacon slot number have more transmission opportunities is addressed by introducing the reference point. Simulation results are given to demonstrate that a DAP can improve the throughput and reduce the packet loss rate.

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