• Transactions on Electrical and Electronic Materials
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• 제16권1호
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• pp.34-36
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• 2015

Amorphous SiZnSnO(SZTO) thin film transistors(TFTs) have been fabricated by RF magnetron sputtering process, and they were annealed in air and in wet ambient. The electrical performance and the structure were analyzed by I-V measurement, XPS, AFM, and XRD. The results showed improvement in device performance by wet annealing process compared to air annealing treatment, because free electron was shown to be increased due to reaction of oxygen and hydrogen generating oxygen vacancy. This is understood by the generation of free electrons. We expect the wet annealing process to be a promising candidate to contributing to high electrical performance of oxide thin film transistors for backplane device applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.185-188
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• 1997

The influence of slow cooling and annealing time in $O_2$ during melting and growth step in MPMG process on J$_{c}$ was investigated. Through the measurement of J$_{c}$ SEM and XRD, it can be observed that the critical characteristics were related with the slow cooling time and annealing time in 02 for melting and growth step of MPMG process. The distribution of critical current density with slow cooling time was the porabolic form and the value of J. was the highest at the 40 hour slow cooling time. And also, the value of J$_{c}$, along the annealing time in $O_2$ in the case of the slow cooling time 40 hour was inclined to increase with annealing time. Consequently, it can be suggested that proper slow cooling titre and annealing time along slow cooling in MPMG process be important to improve the critical characteristics.stics.

• 소성∙가공
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• 제13권3호
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• pp.205-210
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• 2004

The waveguide Bragg gratings have been fabricated by the phase-mask method. An excimer laser with maximum 600mJ output pulse energy and uniform phase masks have been used. Hydrogen loading is often used for enhancing the uv photosensitivity of the core, however, the resultant gratings show significant aging effect. In the present study, high temperature thermal annealing process has been investigated to obtain thermal gratings and process parameters are deduced.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.113-114
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• 2008

Conventional furnace annealing (CFA) for activating Mg-doped p-type GaN films had been performed in pure $N_2$ ambient. All sample activated the same gas ambient. The annealing process change temperature: the first process is performed at $550^{\circ}C$ for 10 min. but, the first process is the same bulk. From second to five process increase activation temperature to change $50^{\circ}C$ and annealing time keeping for 10 min. It is found that the samples characteristic measure hall measurement. Similar results were also evidenced by photoluminescence (PL) measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• 한국자기학회지
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• 제25권2호
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• pp.47-51
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• 2015

이 연구에서는 DC스퍼터링(DC Magnetron Sputtering)방식으로 제작 된 MgO 터널 장벽층을 갖는 자기터널접합을 급속 열처리 방식(Rapid Thermal Annealing)을 이용하여 열처리 공정 중의 구조적, 조성적 변화 및 스핀 수송 특성의 변화를 연구하였다. 본 연구를 통하여 급속 열처리 방식이 기존 일반적인 열처리 방식에 비하여 높은 터널링자기저항비를 얻을 수 있다는 것을 발견하였다. 또한, 열처리 시간의 단축을 통하여 Mn, Ta, Ru 등의 내부물질의 인접한 층으로의 확산을 억제할 수 있다는 것을 알 수 있었다. 유의미한 데이터를 수집하기 위하여 다양한 열처리 온도 조건과 시간조건에서 급속 열처리를 실시 한 후 자기 터널 접합의 전, 자기적 특성을 관찰하였다. 이러한 특성 변화는 향후 보다 우수하고 안정적인 자기적 특성과 열적 안정성을 갖는 자기터널접합 제작을 위해 다양하게 응용될 수 있다고 생각된다.

• 한국진공학회지
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• 제16권5호
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• pp.343-347
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• 2007

Glass disk상에 대향 타겟식 스퍼터링(Facing Target Sputtering) 방식을 이용하여 $0.1\;{\AA}/s$의 낮은 증착속도로 증착시킬 경우 b.c.c. (100)면 우선배향성을 확인하였으며, 그 위에 Pt박막을 증착시킨 경우 hetero-epitaxial 성장에 의해 Pt박막이(111)의 조밀면이 아닌 (100)면이 우선배향 되었다. 이렇게 형성된 Fe (100)/Pt (100) 이층막(두께 각 3 nm)을 $600\;^{\circ}C$ 수소분위기에서 열처리함에 의해 막전체에 걸쳐서 f.c.t. (00n)면을 형성시키는 데 성공하고, 또한 Fe (100)면 상에 Pt 박막을 증착시키는 동안 열처리를 하고 증착 이후 수소분위기에서 열처리함에 의해 열처리 시간 및 온도를 크게 낮출 수 있음을 확인하였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제11권3호
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• pp.178-183
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• 2011

The deterministic annealing-based clustering algorithm is an EM-based algorithm which behaves like simulated annealing method, yet less sensitive to the initialization of parameters. Pairwise clustering is a kind of clustering technique to perform clustering with inter-entity distance information but not enforcing to have detailed attribute information. The pairwise deterministic annealing-based clustering algorithm repeatedly alternates the steps of estimation of mean-fields and the update of membership degrees of data objects to clusters until termination condition holds. Lacking of attribute value information, pairwise clustering algorithms do not explicitly determine the centroids or medoids of clusters in the course of clustering process or at the end of the process. This paper proposes a method to identify the medoids as the centers of formed clusters for the pairwise deterministic annealing-based clustering algorithm. Experimental results show that the proposed method locate meaningful medoids.

• 한국재료학회지
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• 제13권11호
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• pp.721-724
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• 2003

A Fe-Si-B-Ni amorphous alloy manufactured by one roll melt-spinning method showed the crystallization temperature difference of a maximum $10^{\circ}C$ according to each lot. This temperature difference had a considerable influence on the annealing process to be conducted for obtaining the proper inductance of the alloy. The proper annealing temperature of the alloy was $480^{\circ}C$ and the annealing time increased as the crystallization temperature increased. The activation energy measured by Kissinger method increased as the crystallization temperature increased. Therefore, the annealing process must be adjusted by the crystallization temperature difference of the amorphous alloy.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.383-386
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• 1988

In MOS integrated circuits, annealing after oxidation process is necessary to improve physical properties of silicon dioxide. With subsequent annealing in inert gases such as nitrogen or argon, and excess silicon bond is allowed time to complete the oxidation and surface charge density is reduced. In this paper, we will present effects of the rapid thermal annealing on silicon dioxide. In order to evaluate characteristics of silicon dioxide, we analyzed C-V curve dependent on annealing time and temperature, and presented variation of fixed oxide charge.