• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.3
• /
• pp.160-165
• /
• 2009

A 12b 2 MS/s cyclic ADC processing 3.3 Vpp single-ended rail-to-rail input signals is presented. The proposed ADC demonstrates an offset voltage less than 1 mV without well-known calibration and trimming techniques although power supplies are directly employed as voltage references. The SHA-free input sampling scheme and the two-stage switched op-amp discussed in this work reduce power dissipation, while the comparators based on capacitor-divided voltage references show a matched full-scale performance between two flash sub ADCs. The prototype ADC in a $0.18{\mu}m$ 1P6M CMOS demonstrates the effective number of bits of 11.48 for a 100 kHz full-scale input at 2 MS/s. The ADC with an active die area of $0.12\;mm^2$ consumes 3.6 m W at 2 MS/s and 3.3 V (analog)/1.8 V (digital).

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.199-203
• /
• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.371-374
• /
• 2013

In this paper, a sensor node circuit using solar energy harvesting is proposed. PMU(Power Management Unit) manages the energy converted from a solar cell. In order to supply a constant voltage to the sensor node, an LDO (Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter). The circuit has been designed in 0.35um CMOS process.

• Journal of Powder Materials
• /
• v.19 no.4
• /
• pp.297-303
• /
• 2012

In this study, voltammetry system for realizing high sensitivity nano-labeled sensor of detecting heavy metals was designed, and optimal system operating conditions were determined. High precision digital to analog converter (DAC) circuit was designed to control applied unit voltage at working electrode and analog to digital converter (ADC) circuit was designed to measure the current range of $0.1{\sim}1000{\mu}A$ at counter electrode. Main control unit (MCU) circuit for controlling voltammetry system with 150 MHz clock speed, main memory circuit for the mathematical operation processing of the measured current value and independent power circuit for analog/digital circuit parts to reduce various noise were designed. From result of voltammetry system operation, oxidation current peaks which are proportional to the concentrations of Zn, Cd and Pb ions were found at each oxidation potential with high precision.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.129-140
• /
• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Journal of IKEEE
• /
• v.2 no.2 s.3
• /
• pp.278-284
• /
• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.5
• /
• pp.1447-1453
• /
• 2014

This paper proposes the new method based on the availability of three points measurement and convexity of photovoltaic (PV) curve characteristic at the maximum power point (MPP). In general, the MPP tracking (MPPT) function is the important part of all PV systems due to their power-voltage (P-V) characteristics related with weather conditions. Then, the analog-to-digital converter (ADC) and low pass filter (LPF) are required to measure the voltage and current for MPPT by the digital controller, which is used to implement the PV power conditioning system (PCS). The measurement and quantization error due to rounding or truncation in ADC and the delay of LPF might degrade the reliability of MPPT. To overcome this limitation, the proposed method is proposed while improving the performances in both steady-state and dynamic responses based on the detailed investigation of its properties for availability and convexity. The performances of proposed method are evaluated with the several case studies by the PSCAD/EMTDC$^{(R)}$ simulation. Then, the experimental results are given to verify its feasibility in real-time.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.2
• /
• pp.355-358
• /
• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.606-608
• /
• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Journal of Advanced Navigation Technology
• /
• v.23 no.4
• /
• pp.316-321
• /
• 2019

In this paper, by applying the constant current principle we develop an impedance measurement system which can measure the high precision impedance of various electric materials by using microprocessor. This measurement system board has an interface device for acquiring digital data from an external device including an impedance measuring device, and system software is also developed by a firmware program executed on such an embedded board. It can measure the high precision impedance of a specific band with 1/32768 precision by using 15-bit ADC(analog to digital converter) and calculate it to the five digits to the right of the decimal point(fraction part). Data is transmitted through a USB interface of a general computer and a measuring device to manage digital data. An impedance measurement system equipped with a communication function capable of a more general and easy-to-use interface than other equipment is developed and verified.