• Title/Summary/Keyword: Analog-to-Digital(A/D)

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High-Speed Digital/Analog NDR ICs Based on InP RTD/HBT Technology

  • Kim, Cheol-Ho;Jeong, Yong-Sik;Kim, Tae-Ho;Choi, Sun-Kyu;Yang, Kyoung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.3
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    • pp.154-161
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    • 2006
  • This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

A/D Converter for Digital Voltmeter (계수형 전압계를 위한 A/D 변환기)

  • No, Hong-Jo;Gang, Jeong-Su;Lee, Gwon-Ha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.8 no.5
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    • pp.1-9
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    • 1971
  • An analog to digital converter Ivhich is applicable to mass production of digital multimeter is developed. The solid state digital instrument has accuracy $\pm$0.1% of feading $\pm$1 digit over 1 mV to 1000 volts with high input impedance and automatic function. All possibility to affect the distortion of A/D converter is tudied. As a result, useful linearity with high temperature stability of integrating waveforms is achieved by the very simplified circuit configuration to assure the proposed accuracy under various ambient condition.

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A 1.2V 90dB CIFB Sigma-Delta Analog Modulator for Low-power Sensor Interface (저전력 센서 인터페이스를 위한 1.2V 90dB CIFB 시그마-델타 아날로그 모듈레이터)

  • Park, Jin-Woo;Jang, Young-Chan
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.786-792
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    • 2018
  • A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

A Design of Analog Front-End for Noncoherent UWB Communication System

  • Yong Moon Kwan-Ho;Choi Sungsoo;Oh Hui Myong;Kim Kwan-Ho;Lee Won Cheol;Shin Yoan
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.77-81
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    • 2004
  • In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

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A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

16 Channel Strain Gauge Measuring Ubiquitous System Development (유비쿼터스 지향의 16채널 스트레인 게이지 계측 시스템 개발)

  • Jang, Soon-Suk;Kim, Kyung-Suk;Won, Yong-Ill;Kim, Dae-Gon
    • Journal of Institute of Control, Robotics and Systems
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    • v.12 no.9
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    • pp.912-917
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    • 2006
  • A strain gauge weight measuring instrumentation system was designed with RF sensor network facilities. In the sensor module system data conversion and a series of signal processing were totally equipped. 16 strain gauges are incoming sensors and each output of the strain gauge was amplified and filtered for proper analog signal processing. Several measuring instrumentation OP amps and general purposed OP amps were used. 12 bits A/D converters converted analog signals to digital bits and a PIC microprocessor controlled the 16 channels of strain gauges. RF RS232 modules were used for wireless communication between the PIC microprocessor and an Ethernet host far a remote sensor monitoring system development.

Design of A 12-Bit 100-MHz CMOS Digital-to-Analog Converter (12 비트 100 MHz CMOS 디지털/아날로그 변환기의 설계)

  • Lee, Ju-Sang;Choi, Ill-Hoon;Kim, Gyu-Hyun;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.609-612
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    • 2002
  • In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

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A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications

  • Jeon, Young-Deuk;Cho, Young-Kyun;Nam, Jae-Won;Lee, Seung-Chul;Kwon, Jong-Kee
    • ETRI Journal
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    • v.31 no.6
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    • pp.717-724
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    • 2009
  • This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

A Linear Power Amplifier Design Using an Analog Feedforward Method

  • Park, Ung-Hee;Noh, Haeng-Sook
    • ETRI Journal
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    • v.29 no.4
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    • pp.536-538
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    • 2007
  • We propose and describe the fabrication of a linear power amplifier (LPA) using a new analog feedforward method for the IMT-2000 frequency band (2,110-2,170 MHz). The proposed analog feedforward circuit, which operates without a pilot tone or a microprocessor, is a small and simple structure. When the output power of the fabricated LPA is about 44 dBm for a two-tone input signal in the IMT-2000 frequency band, the magnitude of the intermodulation signals is below -60 dBc and the power efficiency is about 7%. In comparison to the fabricated main amplifier, the magnitude of the third intermodulation signal decreases over 24 dB in the IMT-2000 frequency band.

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10-Bit 200-MS/s Current-Steering DAC Using Data-Dependant Current-Cell Clock-Gating

  • Yang, Byung-Do;Seo, Bo-Seok
    • ETRI Journal
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    • v.35 no.1
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    • pp.158-161
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    • 2013
  • This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.