• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.378-380
• /
• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• IEMEK Journal of Embedded Systems and Applications
• /
• v.14 no.1
• /
• pp.33-41
• /
• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Nuclear Engineering and Technology
• /
• v.54 no.6
• /
• pp.2037-2047
• /
• 2022

The contribution of degraded human performance (e.g., human errors) is significant for the safety of diverse social-technical systems. Therefore, it is crucial to understand when and why the performance of human operators could be degraded. In this study, the occurrence probability of human errors was empirically estimated based on the complexity of proceduralized tasks. To this end, Logistic regression analysis was conducted to correlate TACOM (Task Complexity) scores with human errors collected from the full-scope training simulator of nuclear power plants equipped with analog devices (analog environment). As a result, it was observed that the occurrence probability of both errors of commission and errors of omission can be soundly estimated by TACOM scores. Since the effect of diverse performance influencing factors on the occurrence probabilities of human errors could be soundly distinguished by TACOM scores, it is also expected that TACOM scores can be used as a tool to explain when and why the performance of human operators starts to be degraded.

• Journal of Advanced Navigation Technology
• /
• v.18 no.3
• /
• pp.229-235
• /
• 2014

This paper presents the Doherty power amplifier with a digitally controlled analog predistorter circuit of Scintera Corp. to produce high power efficiency and high linearity performance. The analog predistorter improves the linearity performance because of controlling amplitude and phase values of input signal in order to improve intermodulation performance of power amplifier. Also, the power amplifier is designed by the Doherty technology to obtain the high efficiency performance. To validate the Scintera's analog predistorter, we are implemented the power amplifier with Doherty method at center frequency 2150 MHz. Compared with the balanced amplifier, the power amplifier is improved above 11% enhanced efficiency and more than 15 dB ACPR improvement.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1003-1006
• /
• 2003

본 논문에서는 sub-micron 소자에서 SCE(Short Channel Effect) 억제를 위한 Halo 와 SSR(Super Steep Retrograde Well) 적용에 따른 analog 특성의 열화를 석하고 이를 개선하기 위해 Twist 이온주입과 In, Sb Halo 를 채택하였다. Analog 특성은 CMOS 의 amplifier 과 Comparator 로의 사용을 고려해 Drain Rout과 Early voltage를 이용해 나타내었으며 Digital 성능을 함께 고려하였다. 실험결과 NMOS 의 경우 45 twist Halo 조건에서, PMOS의 경우 As보다 Sb를 Halo 로 적용하는 경우 더 우수한 analog 특성을 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.3
• /
• pp.459-468
• /
• 2015

In this paper, we consider an uplink multiuser hybrid beamforming system where an access point (AP) communicates with multiple users simultaneously. The performance of the uplink multiuser hybrid beamforming system depends on the effective channel which is given by the product of the channel matrix and the analog beams. Therefore, to maximize the performance, we need to obtain the channel information and then select the analog beams appropriately by using the acquired channel information. In this paper, we propose the channel estimation method and low complexity analog beam selection algorithm for the uplink multiuser hybrid beamforming system. Additionally, our analysis shows that the proposed low complexity analog beam selection algorithm provides much less complexity than the optimum analog beam selection algorithm. From the numerical results, we confirm that the proposed low complexity analog beam selection algorithm has little performance degradation in spite of much less complexity than the optimum analog beam selection algorithm under the equal system configuration.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.1
• /
• pp.66-74
• /
• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.1C
• /
• pp.77-86
• /
• 2010

In this paper, we present a noncoherent IR-UWB (Impulse Radio-Ultra Wide Band) ranging system with an AFE (Analog Front End) composed of a simple integrator and an 1-bit ADC (Analog-to-Digital Converter), and define AFE characteristics affecting the ranging performance. This system is realistic and easy to implement, since the integrator simply accumulates signal energies and the simple 1-bit ADC is applied instead of the multi-bit ADCs for coherent IR-UWB systems. On the other hand, its ranging accuracy is largely affected channel environments such as noise, multipath fading and so on, since the noncoherent receiver simply squares and integrates the received signals. However, despite these practical importances, there are few conventional researches on the performance analysis according to AFE characteristics in IR-UWB ranging systems. To this end, we analyze in this paper ranging performance according to AFE characteristics for the noncoherent IR-UWB ranging system in various wireless channel environments, and through these results we also present system parameters to be considered in UWB hardware designs.

• Journal of IKEEE
• /
• v.24 no.4
• /
• pp.1028-1033
• /
• 2020

The existing in-band interference reduction method recommends the physical separation distance between wireless devices and interference signals, and the interference can be suppressed through the separation distance. If the in-band interference signals can be reduced in a wireless device, a margin can be given to the physical separation distance. Since there is an effect of extending the receiver dynamic range of receivers, it is highly useful for interference reduction and improvement method. In this paper, the structure of an in-band analog IRM(Interference Reduction Module) is proposed and the design and implementation of the proposed analog IRM are described. To design an analog IRM, the interference reduction performance according to the delay mismatch, phase error and the number of delay lines that affect the performance of the analog IRM was simulated. The proposed analog IRM composed of 16 delay lines was implemented and the implemented IRM has the interference reduction performance of about 10dB for a 5G(NR-FR1-TM-1.1) signal having a 40MHz bandwidth at a center frequency of 3.32GHz. The analog IRM proposed in this paper can be used as an in-band interference canceller.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.149-152
• /
• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.