• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1758-1763
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• 2013

This paper is a study on the performance of the stable cascading BPF. There are generally two methods of designing IIR filter, which are a direct method and an indirect one. The indirect design method that is transformed into the BPF by frequency transformation using the prototype analog LPF which is satisfied for designing specifications is applied to this study. As typical prototype analog LPFs, there are the Butterworth filter, the Chebyshev filter and the elliptic filter. In this study, we connect the frequency transformed BPFs (to the cascade form) which have been converted from the stable Butterworth filter and Chebyshev filter. Three classified simulations are conducted in this study, which are the cascading Butterworth BPF Only, the cascading Chebyshev BPF Only and the cascading Butterworth and Chebyshev BPFs. As a result of the simulation, this study shows that a ripple size of the cascading Chebyshev BPF Only is about 1[dB] smaller than that of the cascading Butterworth and Chebyshev BPFs and also the skirt characteristic of the cascading Chebyshev BPF in the transition band is most outstanding and has the widest bandwidth. The result of performance comparison shows the validity of specifications required in the workplace.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.11-21
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• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.6
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• pp.292-298
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• 2006

Because of the high cost for the active power filter, passive filters have been widly used to eliminate harmonic currents of nonlinear load and can also improve the power factor. They are not often optimal filters because the passive filters are designed under the fixed load conditions. In this paper we proposed the method which only the necessary harmonic filters are operated by detecting the various harmonic current components. We presents the new control method of passive filter selection type with the relay control circuit which is consist of analog GIC, comparater, flip-flop and etc. By the experimental results using the proposed system for the rectifier load, we concluded that the researched method is cost effective and the performance is better than the passive filter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.84-90
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• 2005

In Korea, transition to digital TV broadcasting started at the metropolitan Seoul area and has expanded to the metropolitan area in 2004. However, until 2010 analog NTSC broadcasting will co-exist with digital TV. In this situation, digital TV may have the same channel as an analog NTSC broadcasting. To remove the effect of the analog NTSC intereference, DTV receivers adopt an NTSC rejection filter. In this paper, analysis on properties of the filter, such as a rejection property and noise performance degradation, is presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.