• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.692-698
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• 1986

To fabricate digital I\ulcorner devices which are compatible with analog devices in a chip, phosphorus is implanted in the buried layer of I\ulcorner part which has already been diffused with arsenic impurity. Experimental results show that the muminim propagation delay time of I\ulcorner ring oscillator is 16-18 ns when the upward current gain of I\ulcorner transistor is 6-10.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.43-49
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• 2000

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of Korean Electronics
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• v.3 no.2
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• pp.97-109
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• 1983

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.22-27
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• 1996

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.2
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• pp.22-28
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• 1967

The Reactor transient and steady state Response Problem is not always satisfied in automatic control to insure safe operation, because all physical systems are nonlinear to some region such as the deadzone of relay and the backlash of gear. The study for nonlinear control system is described by the applying of analog computer with the parameters given by the argonne advanced Research Reactor.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.155-165
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• 1994

An analog neural network circuit of rhigh density integration is introduced. It's prototype chip is designed in 3 by 3 mm2 die. It uses only one MOSFET to implement a synapse. The number of synapses per neuron can be expanded by cascading several chips. The influence of nonlinearity in synapses is analyzed. A formalization of the back propagation which can be applied to this circuit is shown. Some simulation results are shown and disscussed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.633-634
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• 2006

A new specification-based analog and mixed-signal test technique using high performance current sensors is proposed. The proposed technique using current sensors built in external ATE has little hardware overhead in circuit under test and high testability without time consuming operation of test point placement algorithm.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.66-73
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• 1993

This paper presents an analog circuit implementation and experimental resuls of the Hopfield type neural network. The proposed architecture enables the reconfiguration betwewn feedback and feedforward networks and employs new circuit designs for the weight supply and storage, analog multilier, nd current-voltage converter, in order to achieve area efficiency as well as function al versatility. The layout design of the eight-neuron neural network is tested as an associative memory to verify its applicability to real world.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.