• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.577-578
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• 2008

This paper proposes new analog ZQ calibration scheme. Proposed analog ZQ calibration scheme is for minimizing the reflection which degrade the signal integrity. And this scheme is for minimizing CIO capacitance. It is simulated under 1.5v supply voltage and samsung 0.18um process. Power consumption of proposed analog ZQ calibration circuit was improved by 32%. Under all skew, temperature from $30^{\circ}C$ to $90^{\circ}C$ and Monte carlo simulation, quantization error of RZQ(=$240{\Omega}$) is less han 1.07%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• ETRI Journal
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• 제44권5호
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• ETRI Journal
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• 제26권6호
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.541-543
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• 2008

현재 폭넓은 시장을 형성하고 있는 LED는 전 세계적으로 이슈화 되고 있는 친환경 조명기기로 각광받고 있으며, 향후 조명 산업의 50% 이상 시장 점유율을 차지할 것으로 예상된다. 본 논문에서는 Analog Dimming을 이용하여 Single-stage LED 구동 회로를 제안한다. 제안된 회로는 기존 방식과 달리 DC/DC단이 없으므로 가격 경쟁력 및 높은 전력 변환 효율을 확보할 수 있고, 고조파 규제 만족을 위한 역률 보정 기능이 있으며 휘도를 선형적으로 제어할 수 있는 Analog Dimming 기능을 가지고 있다. 최종적으로 제안된 Single-stage LED 구동 회로의 동작 및 Analog Dimming 제어 기법을 소개하고, 시뮬레이션 및 40W급 시작품을 제작, 동작 실험을 통하여 그 타당성을 검증한다.

• Nuclear Engineering and Technology
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• 제53권7호
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• pp.2237-2250
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• 2021

The analog-based Ex-core Neutron Flux Monitoring System (ENFMS) in Korean Nuclear Power Plants (NPPs) has been performing its intended functions successfully for a long time. On the other hand, the primary concern with the extended use of analog systems is the aging effect, such as mechanical failures, environmental degradation, and obsolescence. The transition to a digital-based Man-Machine Interface Systems (MMIS) in Korea and other countries has been accelerating, but some systems are still analog-based IC systems, such as the ENFMS in APR1400 NPPs. Digitalized ENFMS can become a reality using computers and microprocessors owing to the progress in digital electronics and information technology. This paper presents the result of the first phase of the research on the digitalization of the ENFMS signal processing electronics for NPPs operated or produced in Korea. It has two main parts: (1) review engineering bases of ex-core neutron flux monitoring system, including nuclear engineering, instrumentation techniques, and analog and digital signal processing techniques, and (2) analysis of analog signal processing electronics of ENFMS for OPR1000 and APR1400 power plants. They are prerequisite to the second phase of the research which is the detailed implementation of the digitalization.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.193-196
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• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• ETRI Journal
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• 제29권4호
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• 대한전자공학회논문지SP
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• 제47권6호
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• pp.28-38
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• 2010

녹화된 아날로그 영상에 내재하는 잡음을 효과적으로 제거하기 위해서는 잡음의 실제 특성과 정도를 정확히 파악하는 것이 매우 중요하다. 본 논문에서는 실제 방송되는 아날로그 영상을 녹화하여 잡음의 특성을 분석한 후, 녹화된 아날로그 영상을 위한 효과적인 학습기반 잡음개선 방법을 제안한다. 먼저 녹화된 아날로그 영상의 잡음을 분석하여 무시할 수 없는 잡음의 연관성이 존재하는 것을 보임으로써, 전통적인 부가 백색 가우시안 잡음 (AWGN) 모델에 기반을 둔 잡음의 추정과 잡음 제거 방법이 가지는 한계를 설명한다. 또한 잡음의 연관성을 고려한 자기회귀 모델을 이용해서 녹화된 아날로그 영상에 내재하는 잡음을 추정하고 합성할 수 있음을 보이며, 추정된 자기회귀 모델을 이용해 학습기반 잡음제거 기법에 적용함으로써 비디오 잡음을 제거한다. 실험결과는 제안된 방법이 무시할 수 없을 정도로 잡음 연관성을 가진 실제 녹화된 아날로그 영상의 잡음 제거에 효과적으로 활용될 수 있음을 보여준다.