• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.22-28
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• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.52-59
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• 2009

In modern radars, dynamic range requirements far severed due to high CNR(Clutter-to-Noise Ratio) environment operation scenario. ADC spurious signal restricted the required dynamic range. In this paper, receiver gain of active phased array radar dependent on ADC nonlinear characteristic was analyzed. Within limited scope of ADC SFDR which blocks required system dynamic range, ADC dynamic range reaches trade-off with ADC SNR loss. Comparing antenna stage output noise voltage to that of ADC input, receiver gain was mathematically analyzed. Finally the whole contents were explained from the application example.

• Korean Journal of Optics and Photonics
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• v.12 no.3
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• pp.184-189
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• 2001

The design of an ultra fast ellipsometer is suggested. It adopts the division-of-amplitude-photopolarimeter (DOAP) as the polarization state detector. It does not utilize any moving part such as the rotating polarizer(analyzer) or even any electronic modulation part like the piezo-electric phase modulator. Hence the time resolution of the present system is limited only by the response time of the photo-detector and electronic circuit as well as the analog-digital converter. The feasibility of the suggested ultra fast ellipsometer was tested and the response time with nano-second time resolution has been verified. Its future application to the investigation of kinetics including that of the phase-change optical recording media like GezSb2 Tes is discussed. ussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.11-14
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• 2003

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.279-282
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• 2005

A real-time measurement and control system was developed, This system is used for nurses at hospitals to check the residual quantity and changing time of Ringer's solution in nurses' room. Load Cell is utilized as a sensor to check the residual quantity of Ringer's solution, This Load Cell detects the physical changes of Ringer's solution and transfers electronic signal to the amplifier. Amplified analog signal is converted into digital signal by NO converter. Developed Embedded system, which computes these data with microprocess(8052) then makes it possible to monitor the residual quantity of Ringer's solution real-time on a server computer. A Checking system on Residual Quantity of Ringer's Solution Using Load cell cut costs using a simple design for a circuit

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.193-193
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• 2008

Wearable and ubiquitous micro systems will be greatly growing and their related devices should be self-powered in order to avoid the replacement of finite power sources, for example, by scavenging energy from the environment. With ever reducing power requirements of both analog and digital circuits, power scavenging approaches are becoming increasingly realistic. One approach is to drive an electromechanical converter from ambient motion or vibration. Vibration-driven generators based on electromagnetic, electrostatic and piezoelectric technologies have been demonstrated. Among various generator types proposed so far, piezoelectric generator possesses considerable potential in micro system. To overcome low mechanical-to-electric energy conversion, the piezoelectric device should activate in resonance mode in response to external vibration. Normally, the external vibration excretes at low frequency ranging 0.1 to 200 Hz, whereas the resonant frequencies of the devices are fixed as constant. Therefore, keeping their resonant mode in varying external vibration can be one of important points in enhancing the conversion efficiency. We investigated the possibility of use of multi-bender type piezoelectric devices. To match the external vibration frequency with the device resonant frequency, the various devices with different resonant frequency were chosen.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.25-33
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• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.