• Journal of IKEEE
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• v.19 no.4
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.67-74
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• 2004

Differently from an existing analog control, because the digital control includes microprocessor basically, the digital control is enable to monitor internal parameters of DC-DC converter and to control output voltage remotely by communicating with a Windows based PC. These things are impossible in an analog control and there are more advantages in a digital control than an analog control. In this paper, with the advantages mentioned above, the feasibility of digital controlled DC-DC converter in low price is proposed. In order to implement these functions, it is used the inexpensive H8/3672 made by Renesas that has built in AD converters and PWM logic generators. The proposed digital controller is applied to a flyback converter that is designed to output DC 5[V] from DC 20∼30[V] and is remotely controlled to make variable outputs from DC 0[V] to 5[V] above in PC. The PWM controller adopts the PD controller in PID. In the last, the response characteristics of a step reference voltage and in a steady state are experimented to verify the feasibility and the usefulness of the proposed flyback converter that is implemented inexpensively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.35-42
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• 2010

In this study, crosstalk between dominant interconnect pairs in an A/D converter circuit is analyzed in frequency domain and effects of termination conditions on crosstalk are described, based on the practical circuit conditions. An A/D converter circuit is a mixed circuit where both clean and noisy signals coexist such that the circuit probably suffers from distortion by crosstalk. An analog input signal and the reference voltage signal, which dominate the overall conversion performance of the A/D converter circuit, are ready to be distorted by crosstalk and include specific termination conditions, such as non-matching and capacitive termination, respectively. Thus, this study presents the model of crosstalk considering impedance mismatch at both ends and analyzes effects of the practical termination conditions in the analog input and the reference voltage interconnects on crosstalk. A typical circuit configuration of the two interconnects is described and crosstalk including near-end and far-end termination impedances is modeled. Effects of the near-end impedance mismatch in the analog input interconnect and the far-end capacitive termination in the reference voltage interconnect are estimated in the frequency domain by using the model of crosstalk and experiments are performed to confirm the estimated results. Microstrip lines are used as interconnects, involving the increase of loss in high frequencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.799-804
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• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.280-285
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• 2004

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.569-572
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• 2004

This paper presents a 12-Bit 250MHz CMOS current-mode Digital to Analog Converter(DAC) with current scalers and dividers. It consist of 4 MSB current scaler, 4 MLSB current divider, and 4 LSB current divider. The simulation results show a conversion rate of 250MHz, DNL/INL of ${\pm}5LSB/{\pm}7LSB$, die area of $0.55mm^2$ and Power dissipation of 27mW at 3.3V

• Journal of the Semiconductor & Display Technology
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• v.3 no.1
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• pp.1-7
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• 2004

In this paper, we have developed the DC parameters test system which inspects the properties of DC parameters for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC(Analog-to-Digital Converter), DAC(Digital-to-Analog Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. In the comparison of results, the results of the simulation are very similar to the ones of the implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.223-228
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• 2021

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.