Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Low-Power CMOS image sensor with multi-column-parallel SAR ADC

  • Hyun, Jang-Su (School of Electrical Information Communication Engineering, Kangwon National Unversity) ;
  • Kim, Hyeon-June (School of Electrical Information Communication Engineering, Kangwon National Unversity)
  • Received : 2021.07.12
  • Accepted : 2021.07.29
  • Published : 2021.07.31
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Abstract

This work presents a low-power CMOS image sensor (CIS) with a multi-column-parallel (MCP) readout structure while focusing on improving its performance compared to previous works. A delta readout scheme that utilizes the image characteristics is optimized for the MCP readout structure. By simply alternating the MCP readout direction for each row selection, additional memory for the row-to-row delta readout is not required, resulting in a reduced area of occupation compared to the previous work. In addition, the bias current of a pre-amplifier in a successive approximate register (SAR) analog-to-digital converter (ADC) changes according to the operating period to improve the power efficiency. The prototype CIS chip was fabricated using a 0.18-㎛ CMOS process. A 160 × 120 pixel array with 4.4 ㎛ pitch was implemented with a 10-bit SAR ADC. The prototype CIS demonstrated a frame rate of 120 fps with a total power consumption of 1.92 mW.

Keywords

Acknowledgement

This study was supported by 2021 Research Grant from Kangwon National University. This work was also supported by a National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2020R1I1A3074020). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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