• 분석과학
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• 제24권2호
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• pp.105-112
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• 2011

태양전지용 박막 규소나 차세대 반도체용 박막트랜지스터의 원료로 사용 가능한 하이드로폴리실란의 합성과 물성 분석에 관한 연구이다. 이러한 하이드로폴리실란을 유기 치환기가 없는 사염화규소를 사용하여 합성한 것이 가장 큰 특징이며, 일반적으로 알칼리금속을 사용한 환원법으로 유기용매에 가용성인 하이드로폴리실란을 합성하는 최적 조건을 확립하고자 하였으며 하이드로폴리실란 용액은 그 물성을 여러 가지 분석 방법을 사용하여 조사하였으며 또한 열분해 실험을 통해 무정형 또는 다결정성 규소로 전환시킬 수 있음을 확인하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권1호
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• pp.1-11
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• 1999

Hyrdogenated amorphous silicon thin film transistors are used as a pixel switching device of TFT-LCDs and very active research works on a-Si:H TFTs are in progress. Further development of the technology based on a-Si:H TFTs depends on the increased understanding of the device physics and the ability to accurately simulate the characteristics of them. A two-dimensional device simulator based on the realistic and flexible physical models can guide the device designs and their optimizations. A non-uniform finite-difference TFT Simulation Program, TFT2DS has been developed to solve the electronic transport equations for a-Si:H TFTs. In TFT2DS, many of the simplifying assumptions are removed. The developed simulator was used to calculate the transfer and output characteristics of a-Si:H TFTs. The measured data were compared with the simulated ones for verifying the validity of TFT2DS. Also the transient behaviors of a-Si:H TFTs were calculated even if the values of the related parameters are not accurately specified.

• 한국재료학회지
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• 제8권4호
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• pp.359-361
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• 1998

$SiH_{4}$를 반응물질로 사용하여 electron cyclotron resonance plasma enhanced chemical vapor deposition(ECR-PECVD)로 실리콘 기판위에 증착한 수소화 비정질 실리콘(a-Si:H)으로부터 가시 photoluminescence(PL) 가 관찰되었다. a-si:H/Si로 부터의 PL은 다공질실리콘으로부터의 PL과 유사하였다. 급속열처리에 의해 $500^{\circ}C$에서 2분간 산소분위기에서 어닐링된 시편의 수소함량은 1~2%로 줄어들었고 시편은 가시 PL을 보여주지 않았는데 이는 a-Si:H의 PL과정에서 수소가 중요한 역할을 한다는 것을 뜻한다. 증착된 a-Si:H의 두께가 증가함에 따라 PL의 세기는 감소하였다. $SiH_{4}$를 사용하여 ECR-PECVD에 의해 Si상에 증착된 a-Si:H로부터의 가시 PL은 Si과 증착된 a-Si:H막 사이에 증착이 이루어지는 동안에 형성된 수소화실리콘으로부터 나오는 것으로 추론된다.

• Journal of Information Display
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• 제10권3호
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• pp.117-120
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• 2009

A new crystallization method for amorphous silicon, called selective area heating (SAH), was proposed. The purpose of SAH is to improve the reliability of amorphous silicon films with extremely low thermal budgets to the glass substrate. The crystallization time shortened from that of the conventional solid-phase crystallization method. An isolated thin heater for SAH was fabricated on a quartz substrate with a Pt layer. To investigate the crystalline properties, Raman scattering spectra were used. The crystalline transverse optic phonon peak was at about 519 $cm^{-1}$, which shows that the films were crystallized. The effect of the crystallization time on the varying thickness of the $SiO_2$ films was investigated. The crystallization area in the 400nm-thick $SiO_2$ film was larger than those of the $SiO_2$ films with other thicknesses after SAH at 16 W for 2 min. The results show that a $SiO_2$ capping layer acts as storage layer for thermal energy. SAH is thus suggested as a new crystallization method for large-area electronic device applications.

• 한국표면공학회지
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• 제43권1호
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• pp.7-11
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• 2010

Solid phase crystallization (SPC) is a simple method in producing a polycrystalline phase by annealing amorphous silicon (a-Si) in a furnace environment. Main motivation of the crystallization technique is to fabricate low temperature polycrystalline silicon thin film transistors (LTPS-TFTs) on a thermally susceptible glass substrate. Studies on SPC have been naturally focused to the low temperature regime. Recently, fabrication of polycrystalline silicon (poly-Si) TFT circuits from a high temperature polycrystalline silicon process on steel foil substrates was reported. Solid phase crystallization of a-Si films proceeds by nucleation and growth. After nucleation polycrystalline phase is propagated via twin mediated growth mechanism. Elliptically shaped grains, therefore, contain intra-granular defects such as micro-twins. Both the intra-granular and the inter-granular defects reflect the crystallinity of SPC poly-Si. Crystallinity and SPC kinetics of high temperatures were compared to those of low temperatures using Raman analysis newly proposed in this study.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.456-456
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• 2009

Boron doping on an n-type Si wafer is requisite process for IBC (Interdigitated Back Contact) solar cells. Fiber laser annealing is one of boron doping methods. For the boron doping, uniformly coated or deposited film is highly required. Plasma enhanced chemical vapor deposition (PECVD) method provides a uniform dopant film or layer which can facilitate doping. Because amorphous silicon layer absorption range for the wavelength of fiber laser does not match well for the direct annealing. In this study, to enhance thermal affection on the existing p-a-Si:H layer, a ${\mu}c$-Si:H intrinsic layer was deposited on the p-a-Si:H layer additionally by PECVD. To improve heat transfer rate to the amorphous silicon layer, and as heating both sides and protecting boron eliminating from the amorphous silicon layer. For p-a-Si:H layer with the ratio of $SiH_4$ : $B_2H_6$ : $H_2$ = 30 : 30 : 120, at $200^{\circ}C$, 50 W, 0.2 Torr for 30 minutes, and for ${\mu}c$-Si:H intrinsic layer, $SiH_4$ : $H_2$ = 10 : 300, at $200^{\circ}C$, 30 W, 0.5 Torr for 60 minutes, 2 cm $\times$ 2 cm size wafers were used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the laser condition set of 20 ~ 27 % of power, 150 ~ 160 kHz, 20 ~ 50 mm/s of marking speed, and $10\;{\sim}\;50 {\mu}m$ spacing with continuous wave mode of scanner lens showed the correlation between lifetime and sheet resistance as $100\;{\Omega}/sq$ and $11.8\;{\mu}s$ vs. $17\;{\Omega}/sq$ and $8.2\;{\mu}s$. Comparing to the singly deposited p-a-Si:H layer case, the additional ${\mu}c$-Si:H layer for doping resulted in no trade-offs, but showed slight improvement of both lifetime and sheet resistance, however sheet resistance might be confined by the additional intrinsic layer. This might come from the ineffective crystallization of amorphous silicon layer. For the additional layer case, lifetime and sheet resistance were measured as $84.8\;{\Omega}/sq$ and $11.09\;{\mu}s$ vs. $79.8\;{\Omega}/sq$ and $11.93\;{\mu}s$. The co-existence of $n^+$layeronthesamesurfaceandeliminating the laser damage should be taken into account for an IBC solar cell structure. Heavily doped uniform boron layer by fiber laser brings not only basic and essential conditions for the beginning step of IBC solar cell fabrication processes, but also the controllable doping concentration and depth that can be established according to the deposition conditions of layers.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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• pp.77-79
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• 2009

Amorphous/crystalline silicon heterojunction solar cells, TCO/a-Si:H (p)/c-Si(n)/a-Si:H(n)/Al, are investigated. The influence of various parameters for the front structures was studied. We used thin (10 nm) a-Si:H(p) layers of amorphous hydrogenated silicon are deposited on top of a thick ($500{\mu}m$) crystalline c-Si wafer. This work deals with the influence of the a-Si:H(p) doping concentration on the solar cell performance is studied.

• 한국정보통신학회논문지
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• 제5권6호
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• pp.1128-1135
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• 2001

본 논문에서는 HSG형성을 위한 Si$_2$H$_{6}$의 조사와 어닐링을 통한 seeding method를 64Mbit DRAM에 적용하였다. 이 기술을 사용함으로서 인이 도우핑된 Amorphous 실리콘의 전극에 HSG grain 크기를 조절할 수 있었고, 이 새로운 HSG형성조건은 기존의 stack 캐패시터보다 약 2배의 정전용량을 확보할 수 있었다. 이와같은 방법을 이용한 HSG형성에서 인농도, 저장폴리 증착온도 및 HSG의 두께에 대한 공정 최적 조건으로는 각각 3.0-4.OE19atoms/㎤ , 53$0^{\circ}C$ 및 400$\AA$이었다. 이들 최적화된 공정조건으로 64M bit DRAM 캐패시터에 적용시 질화막의 두께 한계는 65$\AA$으로 확인되었다.

• 한국세라믹학회지
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• 제22권1호
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• pp.53-59
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• 1985

Experiments related to nitriding silicon with addition of $Si_3N_4$ have provided information on the effects of such inclusion on the phase relationships of Reaction Bonded Silicon Nitride. In the current work specimens containing 0-25wt% Si3N4 which have 55.5wt% $\alpha$ 4.5wt% $eta$, 40wt% amorphous phase were nitrided for 7-20 hours at 1300-135$0^{\circ}C$ The evaluation of nitridation was per-formed by means of $\alpha$-and $\beta$-phase contents determination in nitrided specimens, In order to observe nitrided region between silicon and silicon nitride scanning electron microscopy was used to study reacted region between silicon and silicon nitride particle. For this purpose semiconductor-grade silicon wafer single crystal was used as a silicon source. The incorporation of small amount of $Si_3N_4$ powder is contributed to enhancing the rate of formation of $\alpha$-phase.

• 대한금속재료학회지
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• 제49권4호
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• pp.321-328
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• 2011

The 30 nm-thick Ni layers was deposited on a flexible polyimide substrate with an e-beam evaporation. Subsequently, we deposited a Si layer using a catalytic CVD (Cat-CVD) in a hydride amorphous silicon (${\alpha}$-Si:H) process of $T_{s}=180^{\circ}C$ with varying thicknesses of 55, 75, 145, and 220 nm. The sheet resistance, phase, degree of the crystallization, microstructure, composition, and surface roughness were measured by a four-point probe, HRXRD, micro-Raman spectroscopy, FE-SEM, TEM, AES, and SPM. We confirmed that our newly proposed Cat-CVD process simultaneously formed both NiSi and crystallized Si without additional annealing. The NiSi showed low sheet resistance of < $13{\Omega}$□, while carbon (C) diffused from the substrate led the resistance fluctuation with silicon deposition thickness. HRXRD and micro-Raman analysis also supported the existence of NiSi and crystallized (>66%) Si layers. TEM analysis showed uniform NiSi and silicon layers, and the thickness of the NiSi increased as Si deposition time increased. Based on the AES depth profiling, we confirmed that the carbon from the polyimide substrate diffused into the NiSi and Si layers during the Cat-CVD, which caused a pile-up of C at the interface. This carbon diffusion might lessen NiSi formation and increase the resistance of the NiSi.