• Journal of the Microelectronics and Packaging Society
• /
• v.23 no.4
• /
• pp.43-48
• /
• 2016

3-Dimensional System in Package (3-D SiP) structure (Amkor calls it mPossum-molded Possum) using double side Surface Mount Technology (SMT) and double side molding was evaluated in order to achieve small/thin form factor as well as good functionality by integration and double side layout. As the new platform on laminate substrate basis, molding process was challenge in mold flow balance at top and bottom side and package warpage control over the overall assembly process. There were two types of different molding process evaluated with 1) 1-step molding which was done at both side at the same time and 2) 2-step molding which was done at the conventional molding process twice. Mold simulation helped to narrow down the material selections and parameters available before actual sample build. There were many challenges for this first trial in design/ parameter and material types but optimized them to enable this structure.

• Journal of the Microelectronics and Packaging Society
• /
• v.23 no.4
• /
• pp.31-34
• /
• 2016

System In Package (SiP) is getting popular and momentum for the recent wearable, IoT and connectivity application apart from mobile phone. This is driven by market demands of cost competitive, lighter and smaller/thinner and higher performance. As one of many semiconducting assembly products, Leadframe product has been widely used for low cost solution, light/ small and thin form factor. But It has not been applied for SiP although Leadframe product has many advantages in cost, size and reliability performance. SiP is mostly based on laminate substrate and technically difficult on Leadframe substrate because of a limitation in SMT performance. In this paper, Leadframe based SiP product has been evaluated about key technical challenges in SMT performance and electrical shield technology. Mostly Leadframe is considered not available to apply EMI shield because of tie-bar around package edge. In order to overcome two major challenges, connection bars were deployed properly for SMT pad to pad and additional back-side etching was implemented after molding process to achieve electrical isolation from outer shield coating. This product was confirmed assembly workability as well as reliability.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.41-45
• /
• 2015

RtMLF (Routable Molded Lead Frame) based on molded substrate has been developed to maximize advantages of both leadframe product which has high thermal and electrical performance and laminate product which accommodates more I/O count and keeps fan-in/fan-out design flexibility. Due to its structural features, RtMLF provided excellent thermal and electrical performance which was confirmed with simulation. The RtMLF samples were manufactured and its reliability analysis was done to evaluate the opportunities of the production and application.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.27-27
• /
• 2003

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2001.11a
• /
• pp.99-107
• /
• 2001

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.5-5
• /
• 2003

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.12-12
• /
• 2003

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.4
• /
• pp.91-95
• /
• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.1
• /
• pp.43-47
• /
• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.17-20
• /
• 2003

The EMC's rheological effects on molding process are evaluated in this study. When considering mold processing for IC packages, the major concerning items in current studies are incomplete fill, severe wire sweeping and paddle shifts etc. To simulate EMC's fast curing rheokinetics with 3D mold flow behavior, one should select appropriate rheometry which characterize each EMC's rheological motion and finding empirical parameters for numerical analysis current studies present the new rheometry with parallel plate rheometry for reactive rheokinetic experiments, the experiment and numerical analysis is done with the commercial higher filler loaded EMC for the case of Thin Quad Plant Packages (TQFP) with package thickness below 1.0 mm. The experimental results and simulation results based on new rheometry matches well in point of the prediction of wire sweep, filling behavior of melt front advancement and void trapping position.