• Title/Summary/Keyword: Algorithm Instruction

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An Assignment Motion to Suppress the Unnecessary Code Motion (불필요한 코드 모션 억제를 위한 배정문 모션)

  • Shin, Hyun-Deok;Lee, Dae-Sik;Ahn, Heui-Hak
    • Journal of Internet Computing and Services
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    • v.9 no.1
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    • pp.55-67
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    • 2008
  • This paper presents the assignment motion algorithm unrestricted for code optimization computationally. So, this algorithm is suppressed the unnecessary code motion in order to avoid the superfluous register pressure, we propose the assignment motion algorithm added to the final optimization phase. This paper improves an ambiguous meaning of the predicate. For mixing the basic block level analysis with the instruction level analysis, an ambiguity occurred in Knoop's algorithm. Also, we eliminate an ambiguity of it. Our proposal algorithm improves the runtime efficiency of a program by avoiding the unnecessary recomputations and reexecutions of expressions and assignment statements.

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New Non-linear Inverse Quantization Algorithm and Hardware Architecture for Digital Audio Codecs (디지털 오디오 코덱을 위한 새로운 비선형 역 양자화 알고리즘과 하드웨어 구조)

  • Moon, Jong-Ha;Baek, Jae-Hyun;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.1C
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    • pp.12-18
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    • 2008
  • This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

Implementation of Multi-Core Processor for Beamforming Algorithm of Mobile Ultrasound Image Signals (모바일 초음파 영상신호의 빔포밍 알고리즘을 위한 멀티코어 프로세서 구현)

  • Choi, Byong-Kook;Kim, Jong-Myon
    • The KIPS Transactions:PartA
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    • v.18A no.2
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    • pp.45-52
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    • 2011
  • In the past, a patient went to the room where an ultrasound image diagnosis device was set, and then he or she was examined by a doctor. However, currently a doctor can go and examine the patient with a handheld ultrasound device who stays in a room. However, it was implemented with only fundamental functions, and can not meet the high performance required by the focusing algorithm of ultrasound beam which determines the quality of ultrasound image. In addition, low energy consumption was satisfied for the mobile ultrasound device. To satisfy these requirements, this paper proposes a high-performance and low-power single instruction, multiple data (SIMD) based multi-core processor that supports a representative beamforming algorithm out of several focusing methods of mobile ultrasound image signals. The proposed SIMD multi-core processor, which consists of 16 processing elements (PEs), satisfies the high-performance required by the beamforming algorithm by exploiting considerable data-level parallelism inherent in the echo image data of ultrasound. Experimental results showed that the proposed multi-core processor outperforms a commercial high-performance processor, TI DSP C6416, in terms of execution time (15.8 times better), energy efficiency (6.9 times better), and area efficiency (10 times better).

Design & Verification of 16 Bit RISC Processor (16 비트 RISC 프로세서 설계 및 검증)

  • Jung, Seung-Pyo;Song, Seung-Won;Lee, Dong-Hoon;Kim, Kang-Joo;Cho, Koon-Shik;Park, Ju-Sung
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.423-424
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    • 2008
  • The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

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Construction of a Student-Generated Algorithm for Fraction Measurement Division (분수나눗셈을 해결하기 위한 학생들의 자기-생성 알고리듬 구성에 관한 연구)

  • Shin, Jae-Hong
    • School Mathematics
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    • v.12 no.3
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    • pp.439-454
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    • 2010
  • This study presents how two eighth grade students generated their own algorithms in the context of fraction measurement division situations by modifications of unit-segmenting schemes. Teaching experiment was adopted as a research methodology and part of data from a year-long teaching experiment were used for this report. The present study indicates that the two participating students' construction of reciprocal relationship between the referent whole [one] and the divisor by using their unit- segmenting schemes and its strategic use finally led the students to establish an algorithm for fraction measurement division problems, which was on par with the traditional invert-and-multi- ply algorithm for fraction division. The results of the study imply that teachers' instruction based on understanding student-generated algorithms needs to be accounted as one of the crucial characteristics of good mathematics teaching.

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Method of Multi Thread Management based on Shader Instruction for Mobile GPGPU (GPGPU를 위한 쉐이더 명령어기반 멀티 스레드 관리 기법)

  • Lee, Kwang-Yeob;Park, Tae-Ryong
    • Journal of IKEEE
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    • v.16 no.4
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    • pp.310-315
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    • 2012
  • This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.

The development of CAl Courseware for Basic Life Support - Centered on the Foreign-Body Airway Obstruction in Adult- (기본 인명구조술 교육을 위한 CAI 코스웨어 개발 - 성인의 이물질에 의한 기도폐쇄를 중심으로 -)

  • Kim, Mi-Seon
    • The Korean Journal of Emergency Medical Services
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    • v.7 no.1
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    • pp.109-118
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    • 2003
  • With the rapid development of information and communication technology, a lot of multi-media learning programs are being developed and reported in the field of Emergency medicine both home and abroad. In this connection, this study was aimed at developing a foreign-body airway obstruction courseware in adults for EMT. The development period of CAI courseware lasted from May 2003 through November 2003. Among CAI courseware patterns, private instruction and repeat practice and simulation patterns were used as an instruction-learning strategy. The learning contents of the CAI courseware consisted of five chapters concerning (1) A relief of partial FBAO in the responsible victim, (2) A relief of complete FBAO in the responsible victim, (3) In case of unconsciousness in the responsible victim without removing all foreign body, (4) In case of consciousness in all victims after getting removed all foreign body and (5) A complete airway obstruction in victims without consciousness on the basis of assess responsiveness and the degree of airway obstruction. The way to use this courseware, with just a click on one specific chapter, was developed to proceed a course with progressive algorithm, a method of solving problems by choosing one between two situations. A characteristic of this CAI courseware is the enhanced efficiency of an instruction-learning method by providing an opportunity of choice based on situations in its effort to encourage learners to use a self-initiated learning method, not one-way method and to enhance problem solving skills among situations. Moreover, this courseware went through the diverse phases such as development, application, feedback in connection with learning process by practicing teachers, so that the courseware could be used frequently in the future. The contents of this courseware were written with the web, so that, if necessary, the contents could be continuously modified and complemented and handed out in the form of CD-ROM. This study indicates that the development of a variety of CAI courseware requires institutional and financial assistance and initiatives reflecting a reality in terms of learning process, technical assistance and resources.

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The Design and Implementation of Two-Way Search Algorithm using Mobile Instant Messenger (모바일 인스턴스 메신저를 이용한 양방향 검색 알고리즘의 설계 및 구현)

  • Lee, Daesik;Jang, Chungryong;Lee, Yongkwon
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.11 no.2
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    • pp.55-66
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    • 2015
  • In this paper, we design and implement a two-way search algorithm that can provide a customized service through the user with real-time two-way communication using a mobile instant messaging service. Therefore, we design and implement the automative search system which enables delivering message to each user mobile terminal from a plurality of relay mobile terminals by utilizing the mobile instant messenger, not to deliver a message from the main server to the mobile instant messenger user directly. Two-way search system using the mobile instant messenger can be immediately collect the user's response is easy to identify the orientation of each user, and thus can be provided to establish a differentiated service plan. Also, It provides a number of services(text, photos, videos, etc) in real-time information to the user by utilizing the mobile instant messenger service without the need to install a separate application. Experiment results, data processing speed of the category processing way to search for the data of the DB server from a user mobile terminal is about 7.06sec, data processing number per minute is about 13 times. The data processing speed of the instruction processing way is about 3.10sec, data processing number per minute is about 10 times. The data processing speed of the natural language processing way is about 5.13sec, per data processing number per minute is about 7 times. Therefore in category processing way, command processing way and natural language processing way, instruction processing way is the most excellent in aspect of data processing speed, otherwise in aspect of per data processing number per minute, the category processing way is the best method.

A Course Scheduling Multi-module System based on Web using Algorithm for Analysis of Weakness (취약성 분석 알고리즘을 이용한 웹기반 코스 스케줄링 멀티 모듈 시스템)

  • 이문호;김태석;김봉기
    • Journal of Korea Multimedia Society
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    • v.5 no.3
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    • pp.290-297
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    • 2002
  • The appearance of web technology has accelerated the role of the application of multimedia technology, computer communication technology and multimedia application contents. Recently WBI model which is based on web has been proposed in the part of the new activity model of teaching-teaming. How to learn and evaluate is required to consider individual learner's learning level. And it is recognized that the needs of the efficient and automated education agents in the web-based instruction is increased But many education systems that had been studied recently did not service fluently the courses which learners had been wanting and could not provide the way for the learners to study the learning weakness which is observed in the continuous feedback of the course. In this paper we propose design of multi-module system for course scheduling of learner-oriented using weakness analysis algorithm. First proposed system monitors learner's behaviors constantly, evaluates them, and calculates his accomplishment and weakness. From this weakness the multi-agent prepares the learner a suitable course environment to strengthen his weakness. Then the learner achieves an active and complete teaming from the repeated and suitable course.

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An Optimal Instruction Fetch Strategy for SMT Processors (SMT 프로세서에 최적화된 명령어 페치 전략에 관한 연구)

  • 홍인표;문병인;김문경;이용석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.5C
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    • pp.512-521
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    • 2002
  • Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.