• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.520-529
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• 2001

Carry-save-adder(CSA) is one of the most effective operation cells in implementing an arithmetic hardware with high performace and small circuit area. An fundamental drawback of the existing CAS applications is that the applications are limited to the local parts of arithmetic circuit that are directly converted to additions. To resolve the limitation, we propose a set of new CSA transformation techniques: optimizing arithmetics with multiplexors, optimizing arithmetics in multiple designs, and optimizing arithmetics with multiplications. We then design a new CSA transformation algorithm which integrates the proposed techniques, so that we are able to utilize CSAs more globally. An extensive experimentation for practical designs are provided to show the effectiveness of our proposed algorithm over the conventional CSA techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.810-820
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• 2001

Conventional binary adder requires a carry propagation to the most significant bit, and leads to serial addition. However, optical adder using a modified signed digit(MSD) number system has been Proposed to reduce the carry propagation chain encountered in binary adder. In this paper, in order to minimize the number of symbolic substitution(SS) rules, nine input patterns were divided into five groups of the same addition results. For recognizing the input reference patterns, serial connections of joint spatial encoded patterns and masks without any other spatial operations are used.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.6 s.312
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• pp.10-16
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• 2006

This paper proposed a carry lookahead (CLA) circuitry design. It was based on dynamic circuit aiming at delay reduction in an addition of BCD coded decimal numbers. The performance of these decimal adders is analyzed demonstrating their speed improvement. Timing simulation on the proposed decimal addition circuit employing $0.18{\mu}m$ CMOS technology yielded the worst-case delay of 0.83 ns at 16-digit. The proposed scheme showed a speed improvement compared to several schemes for decimal addition.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.79-93
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• 1997

This paper presents a linear shift-invariant system euqivalent to morphological dilation for a memoryless uniform source in the sense of the power spectral density function, and comares it with dialtion. This equivalent LSI system is found through spectral decomposition and, for dilation and with windwo size L, it is shown to be a finite impulse response filter composed of L-1 delays, L multipliers and three adders. Th ecoefficients of the equivalent systems are tabulated. The comparisons of dilation and its equivalent LSI system show that probability density functions of the output sequences of the two systems are quite different. In particular, the probability density functon from dilation of an independent and identically distributed uniform source over the unit interval (0, 1) shows heavy probability in around 1, while that from the equivalent LSI system shows probability concentration around themean vlaue and symmetricity about it. This difference is due to the fact that dilation is a non-linear process while the equivalent system is linear and shift-ivariant. In the case that dikation is fabored over LSI filters in subjective perforance tests, one of the factors can be traced to this difference in the probability distribution.

• Journal of Korea Multimedia Society
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• v.10 no.7
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• pp.838-845
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• 2007

In this paper, we propose a modified cubic convolution scaler for the enlargement or reduction of digital images. The proposed method has less computational complexity than the cubic convolution method. In order to reduce the computational complexity, we use the linear function of the cubic convolution and the difference value of adjacent pixels for selecting interpolation methods. We employ adders and barrel shifts to calculate weights of the proposed method. The proposed method is compared with the conventional one for the computational complexity and the image quality. It has been designed and verified by HDL(Hardware Description Language), and synthesized using Xilinx Virtex FPGA.

• Journal of information and communication convergence engineering
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• v.15 no.1
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• pp.62-71
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• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.241-249
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• 2003

Carry lookahead(CLA) circuitry of decimal adders is proposed aiming at delay reduction. The truncation error in calculation of monetary interests may accumulate yielding a substantial amount of errors. Binary Coded Decimal(BCD) additions. for example, eliminate the truncation error in a fractional representation of decimal numbers. The proposed BCD carry lookahead scheme is aiming at the speed improvements without any truncation errors in the addition of decimal fractions. The delay estimation of the BCD CLA is demonstrated with improved performance in addition. Further reduction in delay can be achieved introducing non-weighted number system such as the excess-3 code.