Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

A Practical Synthesis Technique for Optimal Arithmetic Hardware based on Carry-Save-Adders

캐리-세이브 가산기에 기초한 연산 하드웨어 최적화를 위한 실질적 합성 기법

  • 김태환 (한국과학기술원 전자전산학과 전산학전공) ;
  • 엄준형 (한국과학기술원 전자전산학과 전산학전공)
  • Published : 2001.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

Carry-save-adder(CSA) is one of the most effective operation cells in implementing an arithmetic hardware with high performace and small circuit area. An fundamental drawback of the existing CAS applications is that the applications are limited to the local parts of arithmetic circuit that are directly converted to additions. To resolve the limitation, we propose a set of new CSA transformation techniques: optimizing arithmetics with multiplexors, optimizing arithmetics in multiple designs, and optimizing arithmetics with multiplications. We then design a new CSA transformation algorithm which integrates the proposed techniques, so that we are able to utilize CSAs more globally. An extensive experimentation for practical designs are provided to show the effectiveness of our proposed algorithm over the conventional CSA techniques.

캐리-세이브 가산기(CSA)는 빠른 수행과 작은 면적을 가지는 연산 하드웨어 구현에서 가장 효과적으로 사용되는 연산 셀들 중의 하나이다. 현재 CSA 적용기술의 근복적인 약점을 그 적용이 덧셈식으로 직접 변환되는 부분에 해당되는 회로에만 가능하다는 것이다. 이러한 제한점을 극복하기위하여, 우리는 새로운 몇가지 CSA 변환 기법들을 제안한다. 구체적으로 멀티플렉서를 포함한 연산에서의 CSA 변환, 다수 회로를 포함한 연산에서의 CSA 변환, 곱셈 연산을 내포한 연산에서의 CSA 변화를 제안한다. 또한 이러한 기법들을 실제의회로 합성에서 효과적으로 적용하는 통합 알고리즘을 제안한다. 우리는 다양한 실험을 통하여 제시된 기법들에 기반한 우리의 알고리즘의 기존의 CSA 방법들과 비교하여 실제적인 회로 합성에서 매우 효율적임을 보인다.

Keywords

References

  1. D. Gajski, N. Dutt, A. Wu, and S. Lin, High level Synthesis Introduction to chip and System Design), Kulwer Academic Publishers, 1992
  2. R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni Vincente, Logic Minimizaiton Algorithms for VLSI Synthesis, Kulwer Academic Publishers, 1984
  3. R. K. Brayton, R. Rudell, A. L. Sangiovanni Vincente, and A. R. Wang, 'MIS : A Multiplelevel Logic Optimization systems, ' IEEE Transactions on Cmputer Aided Design of Intergrated Circuits and Systems, Vol. CAD-6, pp. 1062-1082, 1987
  4. J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, and Y. Watanabe, 'A Delay Model for logic Synthesis of Continuously Sized networks' Proc. of IEEE International Conference on Computer-Aided Design, pp. 458-462, 1995 https://doi.org/10.1109/ICCAD.1995.480156
  5. S. S. Sapatnekar and W. Chuang, 'Power vs.Delay in Gate Sizing : Conflicting Objectives?,' Proc. of IEEE international Conference on Computer Aided Design, pp. 463-466, 1995 https://doi.org/10.1109/ICCAD.1995.480157
  6. M. Potkonjak and J. Rabaey, 'Maximally Fast and Arbitrarily Fast implementation of Linear Computations,' Proc. of IEEE International Conference on Computer Aided Design), pp. 304-308, 1992
  7. D. Lobo and B. Pangric, 'Redundant Operation Creation : A Scheduling Optimlzation Technique,' Proc. of Design Automation Conference, pp. 775-778, 1991
  8. A. Nicolau and R. Potasma, 'Incremental Tree Height Reduction for high level Synthesis,' Proc. of Design Automation Conference, pp. 770-774, 1991
  9. R. Hartley and A. E. Casavant, 'Tree Height Minimization in pipelined Architectures,' Proc. of IEEE International Conference on Computer Aided Design, pp. 112-115, 1989 https://doi.org/10.1109/ICCAD.1989.76916
  10. R. Hartley and A. E. Casavant, 'Optimized Pipelined Networks of Associative and Computative Operators,' IEEE Transactions on Computer Aided Design of integrated Circuits and Systems, Vol. 13, No. 11, November 1994
  11. K. K. Parhi, 'High Level Algorithm and Architecture Transformations for DSP Synthesis,' Journal of VLSI Signal Processing, No. 9. pp. 121-143, 1995 https://doi.org/10.1007/BF02406474
  12. M. Janssens, F. Catthoor, H. De Man, 'A Specification Invariant Technique for Regularity Improvement between Flow Graph Clusters,' Proc.of European Design Automation Conference, pp. 138-143, 1996 https://doi.org/10.1109/EDTC.1996.494139
  13. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design - A Systems perspective, Addition-Wesley Publishers, 1985
  14. T. Kim, W. Jao, and S. Tjiang, 'Circuit Optimization using Carry Save Adder Cells,' IEEE Transactions on Computer Aided Design of integrated Circuits and Systems, Vol. 17, No. 10, pp. 974-984, Oct. 1998 https://doi.org/10.1109/43.728918
  15. Synopsys Inc., Design Compiler Manual, 1998
  16. P. Paulin and J. Knight, 'High level Synthesis Benchmark Results using a Global Scheduling Algorithm,' Logic and Architecture Synthesis for Silicon compilers, North-Holland, pp. 211-228, 1898
  17. A. C. Parker, J. Pizarro, and M. J. Mlinar, 'MAHA : A Program for Datapath Synthesis,' Proc. of IEEE Design Automation Conference, pp. 461-466, 1986
  18. Synopsys Inc., Behavioral Compiler Manual, 1998