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High-Speed Dynamic Decimal Adder Design  

You, Young-Gap (Department of Information & Communication Engineering, Chungbuk Nat'l University)
Kim, Yong-Dae (Department of Information & Communication Engineering, Chungbuk Nat'l University)
Choi, Jong-Hwa (Department of Information & Communication Engineering, Chungbuk Nat'l University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.43, no.6, 2006 , pp. 10-16 More about this Journal
Abstract
This paper proposed a carry lookahead (CLA) circuitry design. It was based on dynamic circuit aiming at delay reduction in an addition of BCD coded decimal numbers. The performance of these decimal adders is analyzed demonstrating their speed improvement. Timing simulation on the proposed decimal addition circuit employing $0.18{\mu}m$ CMOS technology yielded the worst-case delay of 0.83 ns at 16-digit. The proposed scheme showed a speed improvement compared to several schemes for decimal addition.
Keywords
Decimal adder; Dynamic; CLA;
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