• 혜화의학회지
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• 제20권1호
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• pp.153-160
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• 2011

Objective : The objective of this study is to observe the effect of Pharmacopuncture of Anti-inflammatory Herbal compound(AiC) theraphy on elbow pain Methods : The patients diagnosed as lateral epicondylitis and treated mainly with Anti-inflammatory Herbal compound(AiC). After the application of herbal acupuncture, The NRS and ROM of elbow were assessed. Results & conclusion : Symptoms of the patient such as elbow pain and dysfunction were improved after above treatments. so, it is suggested that oriental medical treatment(Pharmacopuncture of Anti-inflammatory Herbal compound(AiC)) is effective on Tennis elbow.

• 동력기계공학회지
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• 제15권3호
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• pp.58-64
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• 2011

As well known, the friction stir welding is a novel welding process which is a solid state welding process for sheet or plate using the friction stir phenomenon. This paper describes the effect of welding condition such as the rotation speed and the travelling speed during the friction stir welding process on the micro Virkers hardness and the microstructure of friction stir welded joints in AI-7075-T651 plate. From those investigations, the highest hardness of stir zone was observed at the welding condition of SO-3. The microstructures of the friction stir welded joints was not dependent on the welding conditions, but in the SO-4 specimen, the friction stir welding defect like tunnel shape was found in stir zone.

• ETRI Journal
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• 제42권4호
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• pp.465-467
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• 2020

• ETRI Journal
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• 제42권4호
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• pp.468-479
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• 2020

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

• 인터넷정보학회논문지
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• 제21권5호
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• pp.149-157
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• 2020

최근 인공지능에 대한 관심이 높아짐에 따라 인공지능 프로세서를 하드웨어로 구현하는 연구가 활발히 진행되고 있다. 하지만 인공지능 프로세서는 기존에 기능 검증을 위한 프로세서 시뮬레이션 외에 애플리케이션 단계에서 인공지능 프로세서가 해당 애플리케이션에 적합한지에 대한 성능 검증이 추가로 필요하다. 본 논문에서는 인공지능 프로세서를 활용한 애플리케이션 성능 검증과 프로세서의 한계점을 탐색할 수 있는 내장형 인공지능 프로세서를 위한 성능 분석기를 제안한다. 본 논문은 내장형 인공지능 프로세서를 위한 성능 분석기를 구현하기 위하여 기존에 구현된 인공지능 프로세서의 구조를 분석하고 이를 기반으로 인공지능 프로세서를 모사하는 내장형 인공지능 프로세서를 위한 성능 분석기를 구현한다. 내장형 인공지능 프로세서를 위한 성능 분석기를 활용해 이미지 인식, 음성 인식 애플리케이션에서 인공지능 프로세서의 성능 분석 및 한계점을 탐색하고, 제한된 메모리 크기 안에서 인공지능 프로세서의 구조를 최적화한다.

• 한국IT서비스학회지
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• 제18권3호
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• pp.117-128
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• 2019

The remarkable achievements of the artificial intelligence in recent years are also raising awareness about its potential risks. Several governments and public organizations have been proposing the artificial intelligence ethics for sustainable development of artificial intelligence by minimizing potential risks. However, most existing proposals are focused on the developer-centered ethics, which is not sufficient for the comprehensive ethics required for ongoing intelligent information society. In addition, they have chosen a number of principles as the starting point of artificial intelligence ethics, so it is not easy to derive the guideline flexibly for a specific member reflecting its own situation. In this paper, we classify primitive members who need artificial intelligence ethics in intelligent information society into three : Developer, Supplier and User. We suggest a new artificial intelligence ethics, Seoul PACT, with minimal principles through publicness (P), accountability (A), controllability (C), and transparency (T). In addition, we provide 38 canonical guidelines based on these four principles, which are applicable to each primitive members. It is possible for a specific member to duplicate the roles of primitive members, so that the flexible derivation of the artificial intelligence ethics guidelines can be made according to the characteristics of the member reflecting its own situation. As an application example, in preparation for applying artificial intelligence to e-government service, we derive a full set of artificial intelligence ethics guideline from Seoul PACT, which can be adopted by the special member named Korean Government.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1998년도 제14회 학술발표회 논문개요집
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• pp.41-41
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• 1998

Rare earth metal films have been used as a buffer layer for growing ferroelectric t thin film or a seed layer for magnetic multilayer. But when it was deposited on s semiconductor substrates for the application of magneto-optic (MO) storage media, it i is difficult to exactly measure magnetic cons떠nts due to shunting current, and so it n needs to grow metal films on insulator substrate to reduce such effect. Recently, it w was reported that ultra-thin Pt layer were epitaxially grown on A12O:J by ion beam s sputtering in 비떠 high vacuum and it can be used as a seed layer for the growth of C Co-contained magnetic multilayer. In this stu$\phi$, Pt thin film were epi떠xially grown on AI2D3 ($\alpha$)OJ) by RF magnetron s sputtering. The crystalline structure was analyzed by transmission electron microscope ( (TEM) and Rutherford Back Scattering (RBS)/Ion Channeling. In TEM study, Pt was b believed to be twinned on AI잉3($\alpha$)01) su$\pi$ace about Pt(ll1) plane.Moreover, RBS c channeling spectra showed that minimum scattering yield of Pt(111)/AI2O:J(1$\alpha$)OJ) was 4 4% and Pt(11J)/AI2D3($\alpha$)OJ) had 3-fold symmetry.

• ETRI Journal
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• 제42권5호
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• ETRI Journal
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• 제42권6호
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• 정보보호학회논문지
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• 제30권5호
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• pp.835-846
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• 2020

이메일을 통해서 거래처나 경영진을 사칭하여 금전이나 민감한 정보를 탈취하는 BEC(Business Email Compromise) 공격이 빈번하게 발생하고 있다. 이러한 공격 형태는 최근 발생한 무역사기 중 가장 큰 비중을 차지하며 FBI에서 추정 2019년 피해 금액만 약 17억 달러에 이른다. 하지만 이에 비해서 기업들의 대응 실태를 살펴보면 전통적인 SPAM 차단시스템에 의존하고 있어 보다 치밀해져만 가는 BEC 공격에는 사실상 무방비 상태이며, 임직원에 관련 사고를 안내하고 주의를 당부하는 변화관리 수준의 대응에 머물고 있다. 이에 BEC 사고 유형과 방법들을 분석하고, AI를 통한 기업에서의 효과적인 BEC 공격 대응방안을 제안하고자 한다.