• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Korean Journal of Radiology
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• v.22 no.2
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• pp.253-262
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• 2021

Objective: To determine whether the values of hepatic apparent diffusion coefficient (ADC) can differentiate biliary atresia (BA) from non-BA or be correlated with the grade of hepatic fibrosis in infants with cholestasis. Materials and Methods: This retrospective cohort study included infants who received liver MRI examinations to evaluate cholestasis from July 2009 to October 2017. Liver ADC, ADC ratio of liver/spleen, aspartate aminotransferase to platelet ratio index (APRI), and spleen size were compared between the BA and non-BA groups. The diagnostic performances of all parameters for significant fibrosis (F3-4) were obtained by receiver-operating characteristics (ROCs) curve analysis. Results: Altogether, 227 infants (98 males and 129 females, mean age = 57.2 ± 36.3 days) including 125 BA patients were analyzed. The absolute ADC difference between two reviewers was 0.10 mm²/s for both liver and spleen. Liver ADC value was specific (80.4%) and ADC ratio was sensitive (88.0%) for the diagnosis of BA with comparable performance. There were 33 patients with F0, 15 with F1, 71 with F2, 35 with F3, and 11 with F4. All four parameters of APRI (τ = 0.296), spleen size (τ = 0.312), liver ADC (τ = -0.206), and ADC ratio (τ = -0.288) showed significant correlation with fibrosis grade (all, p < 0.001). The cutoff values for significant fibrosis (F3-4) were 0.783 for APRI (area under the ROC curve [AUC], 0.721), 5.9 cm for spleen size (AUC, 0.719), 1.044 x 10^-3 mm²/s for liver ADC (AUC, 0.673), and 1.22 for ADC ratio (AUC, 0.651). Conclusion: Liver ADC values and ADC ratio of liver/spleen showed limited additional diagnostic performance for differentiating BA from non-BA and predicting significant hepatic fibrosis in infants with cholestasis.

• Korean Journal of Radiology
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• v.25 no.6
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• pp.511-517
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• 2024

Objective: To prospectively investigate the influence of the menstrual cycle on the background parenchymal signal (BPS) and apparent diffusion coefficient (ADC) of the breast on diffusion-weighted MRI (DW-MRI) in healthy premenopausal women. Materials and Methods: Seven healthy premenopausal women (median age, 37 years; range, 33-49 years) with regular menstrual cycles participated in this study. DW-MRI was performed during each of the four phases of the menstrual cycle (four examinations in total). Three radiologists independently assessed the BPS visual grade on images with b-values of 800 sec/mm² (b800), 1200 sec/mm² (b1200), and a synthetic 1500 sec/mm² (sb1500). Additionally, one radiologist conducted a quantitative analysis to measure the BPS volume (%) and ADC values of the BPS (ADC_BPS) and fibroglandular tissue (ADC_FGT). Changes in the visual grade, BPS volume (%), ADC_BPS, and ADC_FGT during the menstrual cycle were descriptively analyzed. Results: The visual grade of BPS in seven women varied from mild to marked on b800 and from minimal to moderate on b1200 and sb1500. As the b-value increased, the visual grade of BPS decreased. On b800 and sb1500, two of the seven volunteers showed the highest visual grade in the early follicular phase (EFP). On b1200, three of the seven volunteers showed the highest visual grades in EFP. The BPS volume (%) on b800 and b1200 showed the highest value in three of the six volunteers with dense breasts in EFP. Three of the seven volunteers showed the lowest ADC_BPS in the EFP. Four of the seven volunteers showed the highest ADC_BPS in the early luteal phase (ELP) and the lowest ADC_FGT in the late follicular phase (LFP). Conclusion: Most volunteers did not exhibit specific BPS patterns during their menstrual cycles. However, the highest BPS and lowest ADC_BPS were more frequently observed in EFP than in the other menstrual cycle phases, whereas the highest ADC_BPS was more common in ELP. The lowest ADC_FGT was more frequent in LFP.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.943-946
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• 1989

The channel irregularity of Successive Approximation ADC is very large in comparison with other type of ADCs. This characteristic makes it impossible to apply the Successive Approximation ADC to the field of radiation pulse height analysis or the measurement of probability density function. In this paper, an analysis of differential non-linearity of this ADC-is presented. It is made clear that the small deviation of resistance causes very large differential non-linearity.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.867-870
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• 1999

In this paper, we designed a 8-bit flash ADC, which can be used in fully differential circuits. We adopted a 2-step flash architecture with digital correction. The designed ADC is expected to work at the sampling frequency of 30MHz. We carried out the layout with 0.65${\mu}{\textrm}{m}$ CMOS technology The core size is 1.587mm$\times$1.069mm.

• Journal of the Korean Society of Radiology
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• v.5 no.1
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• pp.37-49
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• 2011

To examine the possible changes in the SNRs, CNRs, and ADC values for lumbar spines with metastasis based on the DW images before and after contrast agent injection taken from metastatic spinal cancer patients using a 1.5 T MR machine. The quantitative analysis revealed that in case of spinal cancer subjects, both SNRs and CNRs at all of those assessed locations significantly increased on the DWI after contrast agent injection compared to before, while on the ADC map images, SNRs significantly decreased. On the other hand, significantly decreased ADC values at all the assessed locations were found on the ADC map images. With reference to the normal group, significantly increased SNRs were found at all of the assessed locations on the DWI image after injection compared to before, while significantly decreased SNRs were found on the ADC map images. Also, significantly decreased ADC values at all the assessed locations were found on the ADC map images. For the qualitative analysis, after contrast agent injection, significantly increased signal intensities were found at the locations with spinal cancer on the DWI. In contrast, significantly decreased signal intensities were found on the ADC map images. The implication from the results showing that SNR and CNR significantly increased while ADC value significantly decreased at, above, and below the location of metastatic spinal cancer on DWI after contrast agent injection is that DWI obtained after contrast agent injection can be made available for wider application to vertebral disorders.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.