• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1C
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• pp.14-23
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• 2003

This thesis proposes a sigma-delta modulator architecture with 2 Ms/s data rate and 12 bit resolution. A sigma-delta modulate has the features of oversampling and noise shaping. With these features, it can be connected with low resolution A/D converter to achieve higher resolution A/D converter. Most previous researches have been concentrated on high resolution but low data rate applications, e.g. audio applications. But, in order to be applied to various applications such as wireless data communication, researches on sigma-delta modulator architecture for higher data rate are required. The proposed sigma-delta modulator architecture has the sampling rate of 16 times Nyquist rate to achieve high data rate, and consists of a cascade of two 2nd order sigma-delta modulator to get relatively high resolution. The experimental result shows that the proposed architecture achieves 12-bit resolution at 2 Ms/s data rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.182-185
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• 2014

In this paper, the ADC performs research and development for high speed data transfers to minimize the optical delay. Have more $6{\mu}s$ delay in the data signal converting optical repeater transmission system existing there has been a limit on the high-speed data transmission, and signal conversion. The need to develop a new technique to reduce the delay in time within $2{\mu}s$ data signal converted by using this direct conversion system. It is desired the development of the core technologies necessary for the signal transduction component, such as mobile communications LTE, LTE advanced service transport network is established, the delay time $3{\mu}s$ technology for reducing the delay time in the signal converting a revolutionary step is applied in this paper we have developed an ADC.

• Journal of IKEEE
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• v.16 no.3
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• pp.203-210
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. The proposed DC-DC boost converter delivering 3.3V output from a 2.5V input is designed with CMOS $0.3{\mu}m$ technology. It operates at 500kHz and has a maximum power efficiency of 97.3%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06c
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• pp.48-50
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• 2012

정형화되어 있는 데이터를 트리플 형식의 RDF 데이터로 변환하기 위하여 매핑 온톨로지를 제안하며, 이 온톨로지를 이용하여 실제 데이터를 RDF로 변환하는 변환기를 구현하였다. 본 논문에서는 트리플 변환을 위해 수행하는 매핑 작업을 개념화하고, 일반적인 매핑 타입을 정형화하고 제약사항을 설정하여 온톨로지 스키마로 제공한다. 트리플 생성을 위해 사용자가 매핑 내용을 인스턴스로 생성하면, 이를 이용하여 정형화된 데이터를 RDF로 자동 변환하는 변환기를 구현한다. 제안하는 매핑 온톨로지를 이용한 매핑규칙 작업은 온톨로지 편집툴을 활용하여 작업의 편의성을 제공하며 변환 작업의 안내 역할을 할 것이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• Korean Journal of Optics and Photonics
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• v.14 no.3
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• pp.215-218
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• 2003

A 2R O/E/O wavelength converter is useful for bit rate transparency, though it has a limit on cascadability due to timing-jitter accumulation. In this paper, we propose a nonlinear signal model which is more practical than the commonly used sine wave model. With our model, we theoretically analyzed the effects of timing-jitter and the cascadability of a 2R O/E/O wavelength converter. To confirm the theoretical results, we measured the cascadability in a 40-km re-circulation loop for 10 Gb/s signal.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.509-514
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• 2003

Mach-Zehnder interferometric wavelength converters with monolithically integrated semiconductor optical amplifiers (SOA's) have been fabricated and characteristics of wavelength conversion at 10 Gb/s have been investigated for wavelength span of 40 nm. The devices have been achieved by using a butt-joint combination of buried ridge structure type SOA's and passive waveguides. In the integration, a new method has been applied that removes p+InP cladding layer leading to high propagation loss and forms simultaneously the current blocking and the cladding layer using undoped InP. The module packaging has been achieved by using a titled fiber array for effective coupling into the tilted waveguide in the wavelength converter. Using the module, wavelength conversion with power penalty lower than 1 ㏈ at 10 Gb/s has been demonstrated for wavelength span of 40 nm. In addition, it is show that the module can provide 2R (re-amplification, re-shaping) operation by demonstrating the conversion with the negative penalty.