• Journal of Advanced Navigation Technology
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• v.20 no.4
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• pp.361-366
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• 2016

This paper presents an arbitrary impedance transformer with unequal split, based on S- to admittance parameter conversion. When compared even/ odd- mode analysis, the parameter conversion design method constitutes a simple design method to include phase delay information and arbitrary port impedances and asymmetrical configurations. To validate this design method, we designed a 50 to $12.5{\Omega}$ impedance transformer with a 3:1 unequal power split, at an operating frequency of 1 GHz. To implement the proposed impedance transformer, the low impedance transmission lines of calculated result are fabricated by the transmission line connected shunt open stub. Good experimental performances were obtained, in full agreement with simulated results.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.3
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• pp.197-202
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• 2014

The efficiency of a catalytic converter depends on the flow distribution across a system's chemically active substrate. If irregularities or non-uniform flow patterns exist, the system's conversion efficiency decreases, whereas the manufacturing cost increases. Therefore, it is important to analyze the internal flow of a catalytic converter. In this study, flow pattern measurements along the minor axis were recorded at the mid and exit planes of a ceramic honeycomb catalytic converter at flow rates of 37.8 l/s and 94.4 l/s. Flow distributions of the measurement plans were compared with an automotive company's computed velocity profiles. Measurements along the minor axis showed uneven velocity profiles. The ${\upsilon}$-velocity components between the honeycomb bricks were small but somewhat erratic opposite the intake side of the converter, however, they became flatter in measurements recorded near the intake entrance. For almost all velocity values, the computer model suggested velocities greater than the measured values.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.55-55
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• 2001

개의 N과 P채널 EEPROM을 이용하여 A/D 변환기를 설계하였다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 1.2㎛ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10㎷ 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/D 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 37㎼의 전력을 소모하고 동작주파수는 333㎒ 정도인 것으로 관찰되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.220-222
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• 2002

인터넷에서 멀티미디어 서비스 및 고품질의 서비스를 제공하기 위한 다양한 모델들이 제시되고 있다. 기존의 통합화 서비스 (Intserv)나 차별화 서비스 (Diffserv)가 확장성과 종단간의 QoS 보장 측면에서 문제점을 보이면서 최근에는 이들을 통합하려는 시도가 나오고 있다. 그러나 각 모델의 기본 구조가 다르기 때문에 자연스럽게 연결되는 (Seamless) 통합 네트워크을 제시하는데 상당한 어려움이 있다. 본 논문에서는 인터넷에서 종단간의 QoS을 보장하기 위해 통합 모델의 형태를 보이고, 이를 구현하기 위한 프로토콜 변환기를 제안한다. 프로토콜 변환기는 리눅스 기반으로 구현되었다. 프로토콜 변환기를 포함하는 통합 모델에서 패킷 손실율, 데이터 전송율과 같은 네트워크 성능이 향상되었음을 실험을 통해서 보여진다.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.272-278
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• 2007

In this paper, we present an automated API translator for embedded software development based on a model-driven approach. Since MDA(Model Driven Architecture) provides little support for the development of embedded software, we propose a new method which contains the MDA's advantage, automation of implement process, and can solve the problem of real-time overhead. First, we define 'generic APIs' which do not depend on any RTOS's but provide most of typical RTOS services. We can describe RTOS-related behaviors of target application using these generic APIs in a CIC(Common Intermediate Code). Then, we propose a transformation tool for translating a CIC using generic APIs into a C-code for specific RTOS. The proposed API translator converts them into C-code using XML transformation rule which is defined outside. It indicates that an API translator extends to other RTOS's by modifying or adding the transformation rule. From the experiment, we validate the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.