• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.631-634
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• 2002

In this paper we improved that hump occurrence by increased oxidation thickness, and control field oxide recess$(\leq20nm)$, wet oxidation etch time(19HF, 30sec), STI nitride wet cleaning time(99 HF, 60sec + P 90min) and gate pre-oxidation cleaning time(U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.1-8
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• 2009

In this paper, a temperature variation-insensitive power-up detector for use in analog and digital integrated systems has been proposed. To provide temperature-insensitive characteristic, nMOS and pMOS voltage dividers in the proposed power-up detector are made to have zero temperature coefficient by exploiting the fact that the effective gate-source voltage of a MOS transistor can result in mutual compensation of mobility and threshold voltage for temperature independency. Comparison results using a 68-nm CMOS process indicate that the proposed power-up detector achieves as small as 4 mV voltage variation at 1.0 V power-up voltage over a temperature range of $-30^{\circ}C$ to $90^{\circ}C$, resulting in 92.6% reduction on power-up voltage variations over conventional power-up detectors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.85-90
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• 2002

$RuO_2$/GaN and related contacts were investigated for Schottky contacts in GaN-Based optical and electronic devices. We demonstrated that an $RuO_2$ film forms a stable Schottky contact on a GaN layer with a barrier height (${\Phi}_B$) of 1.46 eV and transmittance of 70% in the visible and near UV region. $RuO_2$/GaN Schottky diode showed a breakdown at over -50V and leakage current of only 0.3 nA at -5V. The $RuO_2$/GaN Schottky type photodetector had the UV/Visible rejection ratio of over $10^5$ and the responsivity of 0.23 A/W at 330 nm. The $RuO_2$ gate AlGaN/GaN EFET exhibited high drain current ($I_d$) of 689.3 mA/mm and high transconductance ($g_m$) of 197.4 mS/mm. Cut-Off frequency ($f_t$) and maximum operating frequency ($f_{max}$) were measured as 27.0 GHz and 45.5 GHz, respectively.