• Journal of Digital Convergence
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• v.15 no.6
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• pp.457-466
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• 2017

The present study is to observe changes of health promoting behaviors of obese women by applying 8 weeks of motion-beat on rhythm exercise program. The effects of the obese women's motion-beat in rhythm exercise were summarized in the following conclusions: For changes in their health promoting behaviors, according to the application of motion-beat to the eight-week rhythm exercise, it was noted that the application of motion-beat was effective in the factor of stress management. Therefore, since the exercise applying motion-beat maximizes fun and interest, it has been developed as a program on sports for all, appropriate and efficient for obese women, and it is expected that positive changes in health promoting behaviors can be suggested as a measure for the facilitation of their continuous participation in the exercise.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.533-536
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• 2003

본 논문에서는 전화선을 이용한 고속 홈네트워크인 HomePNA 2.0 시스템에서 HomePNA 2.0 (H2) 프레임을 만들기 위한 프레임 프로세싱 중, 다항식 나누기 연산을 통한 CRC (Cyclic Redundancy Check) 16비트 생성, HCS (Header Check Sequence) 8비트 생성 및 혼화(Scrambling) 처리에 있어서 입력 8 비트를 동시에 병렬 처리함으로써 기존의 1 비트 입력을 LFSR (Linear Feedback Shift Register)를 사용한 다항식 나누기 연산을 수행했을 때보다 빠른 속도로 H2 프레임을 구현하고자 하는 고속 처리 기법을 제시하고 이의 성능을 검증하였다.

• Journal of Broadcast Engineering
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• v.22 no.1
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• pp.42-50
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• 2017

A Bit-depth expansion is a method to increase the number of bit. It is getting important as the needs of HDR (High Dynamic Range) display or resolution of display have been increased because the level of luminance or expressiveness of color is proportional to the number of bit in the display. In this paper, we present effective bit-depth expansion algorithm for conventional standard 8 bit-depth content to display in high bit-depth device (10 bits). Proposed method shows better result comparing with recently developed methods in quantitative (PSNR) with low complexity. The proposed method shows 1db higher in PSNR measurement with 40 times faster in computational time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.99-105
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• 2004

A shared-capacitor charge-sharing ROM (SCCS-ROM) using dummy bit lines is proposed. The SCCS-ROM reduces the bit line swing voltage using the charge-sharing technique of the conventional charge-sharing ROM (CS-ROM). Although the CS-ROM needs three small capacitors per output bit, the proposed SCCS-ROM shares the capacitors so that it needs only three capacitors. The SCCS-ROM implements the capacitors using dummy bit lines. This not only increases noise immunity but also reduces power. A SCCS-ROM with 8K${\times}$15bits implemented in a 0.35${\mu}{\textrm}{m}$ CMOS process. The SCCS-ROM consumes 8.63㎽ at 100MHz with 3.3V The simulation results show that the SCCS-ROM reduces 8.4% power compared to the CS-ROM.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.67-80
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• 1998

논문에서는 프레임릴레이 프로토콜을 사용하는 암호 통신 시스템에 적합한 키 스트림 동기 방식을 제안하였다. 제안된 주소영역의 확장 비트를 이용한 키 스트림 동기 방식은 단위 측정 시간 동안 측정된 프레임릴레이 프로토콜의 주소영역의 확장 비트 정보와 플래그 패턴의 수신률을 이용하여 문턱값보다 적은 경우에 동기 신호와 세션 키를 전송하므로써 종래의 주기적인 동기 방식에서 전송 효율성 저하와 주기적인 상이한 세션 키 발생, 다음 주김까지 동기 이탈 상태로 인한 오류 확산 등의 단점을 해결하였다. 제안된 알고리즘을 데이터 링크 계층의 처리기능을 최소화하여 패킷 망의 고속화가 가능하도록 설계된 프레임릴레이 프로토콜에서 서비스되는 동기식 스트림 암호 통신 시스템에 적용하여 slip rate $10^{-7}$의 환경에서 주기가 Isec인 주기적인 동기 방식에서 요구되는 9.6*10/ sup 6/비트에 비해 6.4*$10^{5}$비트가 소요됨으로써 전송율 측면에서의 성능 향상과 오복호율과 오복호율과 오복호 데이터 비트 측면에서 성능 향상을 얻었다.다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.153-160
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• 2004

In this paper, we propose an efficient bit loading algorithm for IEEE 802.11a wireless LAN systems. While a conventional bit loading algorithm uses the SNR value of each subcarrier, it is very difficult to estimate the exact SNR value in wireless LAN systems due to randomness of AWGN. Therefore, in order to solve this problem our proposed algorithm uses the channel frequency response instead of the SNR of each subcarrier. Through simulation results, we can obtain the performance gain of 3.5∼8㏈ at PER of 10-2 with the proposed bit loading algorithm while the conventional one obtains the performance gain of 0.5∼5㏈ at the same conditions. Also, the increased data rate can be confirmed 63Mbps. After the logic synthesis using 0.3${\mu}{\textrm}{m}$ CMOS technology, the logic gate count for the processor with proposed algorithm can be reduced by 34% in comparison with the conventional one.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.400-411
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• 2017

This study aimed to maximize the effectiveness of motionbeat rhythm exercise on obese women and its applicability in all fields of sports. In addition, this study aimed to propose a plan to promote continuous exercise for people to incorporate as a means to improve healthy lifestyle. The results showed several effects of EEG on health promoting behaviors. Electroencephalogram (Alpha Power) of the left prefrontal cortex showed to have a significant effect on health promotion activities, with respect to stress management, in the motion beat rhythm exercise group. Considering all research findings, we found that the 8-week motion beat exercise can be used as an appropriate and effective social sport program for overweight women as it brings forth positive changes in the prefrontal cortex that maximizes the pleasantness of and interest in health promotion activities relating to stress management. Moreover, we suggest that it can be a method to create an environment for overweight people to continuously participate in exercises by providing results from fun and relaxingactivities, rather than just creating simple physical effects.