• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.5
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• pp.1005-1009
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• 2010

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.608-614
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• 2015

A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.719-727
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• 2016

This paper proposes a unified medium access control (MAC) design methodology and presents the implementation of the IEEE 802.11ac down-link multi-user multi-input and multi-output wireless local area network MAC using the proposed design methodology. The proposed methodology employs unified code for both network simulation and system implementation. Because the unified code closely relates these two processes, the performance of the implemented MAC system can be estimated before implementation. The MAC architecture for an access point implemented using the proposed design methodology is verified on an ARM-based platform, and it is applied to a 65 nm CMOS library.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.415-424
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• 2016

This paper describes a high data rate proximity transmitter design for high resolution smartphone-mirrored display applications. A 2 Gb/s transmitter is designed with a low transmission power of -70 dBm/MHz and a wide bandwidth of nearly 3 GHz. A digital pre-correction method is employed in the transmitter to mitigate the inter-symbol interference problem. A carrier-based digital pulse shaping and a reconfigurable digital envelope generation methods are employed for robust operation by utilizing 20 phases from a 2 GHz phase-locked loop. A 6.5-9.5 GHz transmitter implemented in 65 nm CMOS achieves the maximum data rate of 2 Gb/s, consuming only 7.6 mW from a 1 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• ETRI Journal
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• v.42 no.5
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.7-13
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• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.325-329
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• 2011

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.