• Korean Journal of Optics and Photonics
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• v.9 no.5
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• pp.342-347
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• 1998

We present a theoretical analysis of Gaussian beam propagation in nonlinear Kerr media by using aberration-free approximation and Huygens-Fresnel diffraction integral and obtain a simple analytic formular for Z-scan characteristics. Z-scan experiments are carried out on amorphous $As_2S_3$ thin film and compared with the theory developed, showing good agreement. The sign and the value of ${\gamma}$ have been measured at 633 nm to be $+8.65{\times}10^{-6}\textrm{cm}^2/W$. We also measured the far-field intensity profiles, which confirm again self-focusing effect.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.65-70
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• 2006

Characteristics of thin-film NTC thermal sensors fabricated by micromachining technology were studied as a function of the thickness of membrane. The overall-structure of thermal sensor has a form of Au/Ti/NTC/$SiO_{X}$/(100)Si. NTC film of $Mn_{1.5}CoNi_{0.5}O_{4}$ with 0.5 mm in thickness was deposited on $SiO_{X}$ layer (1.2 mm) by PLD (pulsed laser deposition) and annealed at 873-1073 K in air for 1 hour. Au(200 nm)/Ti(100 nm) electrode was coated on NTC film by dc sputtering. By the results of microstructure, X-ray and NTC analysis, post-annealed NTC films at 973 K for 1 hour showed the best characteristics as NTC thermal sensing film. In order to reduce the thermal mass and thermal time constant of sensor, the sensing element was built-up on a thin membrane with the thickness of 20-65 mm. Sensors with thin sensing membrane showed the good detecting characteristics.

• Journal of the Korean Society of Food Science and Nutrition
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• v.28 no.4
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• pp.810-815
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• 1999

The pectinase treatment conditions for clarification of persimmon vinegar were optimized and monitored by response surface methodology. In clarification of persimmon vinegar by pectinase treatment with variations in temperature, time and concentration, coefficients of determinations(R2) of the models were above 0.91(p<0.05) in turbidity, browning color intensity and tannin content. The turbidity of persimmon vinegar was decreased along with an increase of pectinase treatment temperature. The minimum value of turbidity by pectinase treatment was 0.0021(absorbance at 660nm) in 49.38oC of pectinase treatment temperature, 73.08min of pectinase treatment time and 55.57ppm of pectinase concentration. The minimum value of browning color intensity by pectinase treatment was 0.27(absorbance at 660nm) in 48.39oC, 71.74min and 65.69ppm. The minimum value of total tannin contents by pectinase treatment was 43.72mg/100 ml in 40.05oC, 66.02min and 65.26ppm. The optimum conditions of pectinase treatment that satisfies the least common multiple of turbidity, browning color and tannin content were 40~50oC, 60~70min and 55~70ppm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.117-123
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• 2013

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• Journal of IKEEE
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• v.18 no.2
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• pp.198-205
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• 2014

As the development of information technology, the interests in tiny applications such as wearable devices, portable devices and RFID are increased and the importance of low-area encryption circuit is emphasized. This paper proposes a compact architecture of AES-based encryption circuit suitable for tiny applications. The circuit area is reduced by minimizing storage space and sharing computation resources. The synthesized gate-level circuit using 65nm standard cell library consists of 2,241 gates and two $8{\times}16$-bit SRAMs. It can process data at a rate of 50.57Mbits per second. Therefore, the proposed encryption circuit is suitable for various applications requiring very small encryption circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.877-882
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• 2016

In this paper, a novel CMOS high Q factor 2-port active inductor has been proposed. The proposed circuit is designed by cascading basic gyrator-C structural active inductors and attaching the feedback LC resonance circuit. This LC resonator can compensate parasitic capacitance of transistor and can improve Q factor over wide frequency range. The proposed circuit was fabricated and simulated using 65 nm Samsung RF CMOS process. The fabricated circuit shows inductance of above 2 nH and Q factor higher than 40 in the frequency range of 1~6 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8A
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• pp.821-828
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• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.