Browse > Article
http://dx.doi.org/10.5573/ieek.2013.50.11.117

Low Power Embedded Memory Design for Viterbi Decoder with Energy Optimized Write Operation  

Tang, Hoyoung (School of Electrical Engineering, Korea University)
Shin, Dongyeob (School of Electrical Engineering, Korea University)
Song, Donghoo (School of Nano-Semiconductor, Korea University)
Park, Jongsun (School of Electrical Engineering, Korea University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.11, 2013 , pp. 117-123 More about this Journal
Abstract
By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.
Keywords
Viterbi decoder; Embedded memory; SRAM; Access pattern; Low power operation;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Min Woo Kim and Jun Dong Cho , "A Bit-level ACSU of High Speed Viterbi Decoder", Journal of Semiconductor Technology and Science Vol.6 No.4 pp.240-245, June 2006.
2 W.-L. Su and H. Chiueh, "A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder," in 13th IEEE International Conference on Electronics, Circuits and Systems, ICECS '06, pp. 553-556. Dec. 2006.
3 L. Chen, J. He, and Z. Wang, "Design of Low-Power Memory-Efficient Viterbi Decoder," in 2007 IEEE Workshop on Signal Processing Systems, pp. 132-135, Oct. 2007.
4 Jerrold A. Heller et al, "Viterbi Decoding for satellite and space Communication" IEEE Trans. on communication technology, Vol. 19, no. 5, pp. 835-848, October 1971.   DOI   ScienceOn
5 Leland Chang et al.,"An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches", IEEE Journal of Solid-State circuits, Vol. 43, no.4, April, 2008.
6 J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.   DOI   ScienceOn
7 Jan M.Rabey Anantha Chandrakasan and Borivoje Nikolic, "Digital Integrated Circuits-A Design Perspective", Pearson Education, p, 30-32, 2003.
8 Y. Ren, M. Gansen, and T. Noll, "Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme," in SOC Conference (SOCC), 2012 IEEE International, pp. 224-229, Sept. 2012.
9 S. X. Wang and A. M. Taratorin, Magnetic Information Storage Technology, Academic Press, 1999, ch. 12.
10 B. Jeon and J. Jeong, "Blocking artifacts reduction in image compression with block boundary discontinuity criterion," IEEE Trans. Circuits and Systems for Video Tech., Vol. 8, no. 3, pp. 345-357, June 1998.   DOI   ScienceOn
11 W. G. Jeon and Y. S. Cho, "An equalization technique for OFDM and MC-CDMA in a multipath fading channels, " in Proc. of IEEE Conf. on Acoustics, Speech and Signal Processing, pp. 2529-2532, Munich, Germany, May 1997.