1 |
S. Lin, D. J. Costello, Error Control Coding: Fundamentals and Applications, Prentice- Hall, 1983
|
2 |
H. Lee, "High-speed VLSI architecture for parallel Reed-Solomon decoder", IEEE Trans. VLSI Syst., Vol.11, No.2, pp.288-294, Apr., 2003
DOI
ScienceOn
|
3 |
S. B. Wicker, Error Control Systems for Digital Communication and Storage, Englewood Cliffs, NJ, Prentice-Hall, 1995
|
4 |
J. H. Baek and M. H. SunWoo, "New degree computationless modified Euclid's algorithm and architecture for Reed-Solomon decoder", IEEE Trans. VLSI Syst., Vol.14, No.8, pp.915-920, Aug. 2006
DOI
ScienceOn
|
5 |
Hyeong-Ju Kang, In-Cheol Park, "A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure", IEEE ICASSP, Vol.3, pp.3180-3183, May, 2002
|
6 |
H. Lee, "Modified Euclidean algorithm block for high-speed Reed-Solomon decoder", Electron. Lett., 37, pp. 903-904, 2001
DOI
ScienceOn
|
7 |
S. W. Choi, S. S. Choi, H. Lee, "RS decoder architecture for UWB," IEEE ICACT 2006, pp. 805-808, 2006
|
8 |
H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder", IEEE Trans. Comput., Vol.C-34, No.5, pp.393-403, May, 1985.
DOI
ScienceOn
|
9 |
International Standard, ISO/IEC 26907:2007(E), "Information technology - Telecommunications and information exchange between systems - High Rate Ultra Wideband PHY and MAC Standard
|