• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Journal of information and communication convergence engineering
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• v.15 no.2
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• pp.117-122
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• 2017

Three-dimensional integrated circuits (3D ICs), starting with memory cubes, have entered the mainstream recently. The benefits many predicted in the past are indeed delivered, including higher memory bandwidth, smaller form factor, and lower energy. However, 3D ICs have yet to find their deployment in aerospace applications. In this paper we first present key design tools and methodologies for high performance, low power, and reliable 3D ICs that mainly target terrestrial applications. Next, we discuss research needs to extend their capabilities to ensure reliable operations under the harsh space environments. We first present a design methodology that performs fine-grained partitioning of functional modules in 3D ICs for power reduction. Next, we discuss our multi-physics reliability analysis tool that identifies thermal and mechanical reliability trouble spots in the given 3D IC layouts. Our tools will help aerospace electronics designers to improve the reliability of these 3D IC components while not degrading their energy benefits.

• ETRI Journal
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• v.36 no.4
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• pp.635-642
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• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.867-873
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• 2016

Even if ICS(Interference Cancellation System) repeater is used in wireless communication system, it has the disadvantage that it must have enough distance between Donor and Service antenna to be isolated. In this paper, new ICS repeater integrated antenna with high insolation characteristics is designed. The proposed antenna is fabricated for 800MHz and measured. Bandwidth and gain are optimized by changing the stub lengths near main patch and power divider, and also by changing the size of parasitic patch. The fabricated antenna has a return loss less than -13 dB, a gain over 3 dBi, and an isolation between the donor and the server antennas less than -56 dB from 824~894 MHz for CDMA mobile communication. Therefore, the proposed antenna structure can be applied to eliminate the shadow area and to expand the coverage area for any other wireless communication bands.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.75-76
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• 2016

Even if ICS(Interference Cancellation System) repeater is used in wireless communication system, it has the disadvantage that it must have enough distance between Donor and Service antenna to be isolated. In this paper, new ICS repeater integrated antenna with high insolation characteristics is designed. The proposed antenna is fabricated for 800MHz and measured. Bandwidth and gain are optimized by changing the stub lengths near main patch and power divider, and also by changing the size of parasitic patch. This antenna has a return loss less than -13 dB, a gain over 3 dBi, and an isolation between the donor and the server antennas less than -56 dB from 824~894 MHz for CDMA mobile communication. Therefore, the proposed antenna structure can be applied to eliminate the shadow area and to expand the coverage area for any other wireless communication bands.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.344-350
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• 2011

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.258-267
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• 2016

Three-dimensional integrated circuits (3D ICs) experience die-to-die variations in addition to the already challenging within-die variations. This adds an additional design complexity and makes variation estimation and full-chip optimization even more challenging. In this paper, we show that the industry standard on-chip variation (AOCV) tables cannot be applied directly to 3D paths that are spanning multiple dies. We develop a new machine learning-based model and methodology for an accurate variation estimation of logic paths in 3D designs. Our model makes use of key parameters extracted from existing GDSII 3D IC design and sign-off simulation database. Thus, it requires no runtime overhead when compared to AOCV analysis while achieving an average accuracy of 90% in variation evaluation. By using our model in a full-chip variation-aware 3D IC physical design flow, we obtain up to 16% improvement in critical path delay under variations, which is verified with detailed Monte Carlo simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.36-42
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• 1997

This paper presents a new design technique for performing high quality low bit rate image compression. A hybrid coder(HC) which combines Mean Removed Important Coefficient Selection based JPEG(MR-ICS-JPEG) and Adaptive Vector Quantization (AVQ) is proposed. A new quantization table is developed using the Important Coefficient Selection(ICS) method; the importance of each coefficient is determined using the orthonormal property of the DCT. This quantization table is applied to standard JPEG with mean removal(MR) strategy before processing. This scheme, called MR-ICS-JPEG, produces more than 2 dB enhanced performance in terms of PSNR over standard JPEG. A set of homogeneous codebooks is generated by homogeneous training vectors. Before compression, an image is uniformly divided into 8${\times}$8 blocks. Low detail regions such as backgrounds are roughly coded by AVQ while high detail regions such as edges or curves are finely coded by the proposed MR-ICS-JPEG. This hybrid coder procuces consistently about 3 dB improved performance in terms of PSNR over standard JPEG.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.221-228
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• 2011

This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a$ 0.18-{\mu}m$ CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 $mm^2$ of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 ${\mu}A$ and 40 ${\mu}A$, respectively.