• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.265-271
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• 2008

TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.17-20
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• 2003

The EMC's rheological effects on molding process are evaluated in this study. When considering mold processing for IC packages, the major concerning items in current studies are incomplete fill, severe wire sweeping and paddle shifts etc. To simulate EMC's fast curing rheokinetics with 3D mold flow behavior, one should select appropriate rheometry which characterize each EMC's rheological motion and finding empirical parameters for numerical analysis current studies present the new rheometry with parallel plate rheometry for reactive rheokinetic experiments, the experiment and numerical analysis is done with the commercial higher filler loaded EMC for the case of Thin Quad Plant Packages (TQFP) with package thickness below 1.0 mm. The experimental results and simulation results based on new rheometry matches well in point of the prediction of wire sweep, filling behavior of melt front advancement and void trapping position.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.339-342
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• 2005

We present a new high-frequency equivalent circuit model for 52pin QFP used in typical IC's and extract R, L, and C values of this circuit model using a 3-D E & M field simulator. Futhermore, L and C value variations as a function of Pin number due to the shape differences of the leads have been fitted to 2nd order polynomials in order to extend the applicability of this model.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.194-199
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• 1997

When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.3
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• pp.45-50
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• 2005

A UV camera is being used in various application regions such as industry, medical science, military, and environment monitoring. A ROIC(ReadOut IC) is developed and can read the responses from UV photodiode sensors which are made with III-V nitride semiconductors of GaN series haying high resolution and high efficiency. To design FPA(Focal Plane Array) UV $8{\times}8$ ROIC, the photodiode type sensor devices are modeled as the capacitor type ones. The ROIC reads out signals from the detector at)d outputs sequentially pixel signals after amplifying and noise filtering of them. The ROIC is fabricated using the $0.5{\mu}m$ 2Poly 3Metal N-well CMOS process. And then, it and photodiode array are hybrid bonded by gold stud bumping process using ACP(Anisotropic Conductive Paste). After the packaging, UV images appearing on PC verified the operations of the ROIC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of the Korean institute of surface engineering
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• v.56 no.3
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• pp.180-184
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• 2023

Scholars have proposed wafer-level bonding and three-dimensional (3D) stacked integrated circuit (IC) and have investigated Cu-Cu bonding to overcome the limitation of Moore's law. However, information about quantitative Cu-Cu direct-bonding conditions, such as temperature, pressure, and interfacial adhesion energy, is scant. This study determines the optimal temperature and pressure for Cu-Cu bonding by varying the bonding temperature to 100, 150, 200, 250, and 350 ℃ and pressure to 2,303 and 3,087 N/cm². Various conditions and methods for surface treatment were performed to prevent oxidation of the surface of the sample and remove organic compounds in Cu direct bonding as variables of temperature and pressure. EDX experiments were conducted to confirm chemical information on the bonding characteristics between the substrate and Cu to confirm the bonding mechanism between the substrate and Cu. In addition, after the combination with the change of temperature and pressure variables, UTM measurement was performed to investigate the bond force between the substrate and Cu, and it was confirmed that the bond force increased proportionally as the temperature and pressure increased.