• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2003.11a
• /
• pp.69-72
• /
• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.63 no.12
• /
• pp.1710-1715
• /
• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• 한국정보통신설비학회:학술대회논문집
• /
• 2004.08a
• /
• pp.3-5
• /
• 2004

Balanced input 단을 갖는 IC chip과의 interface를 위하여 2.4GHz 대역의 Balun BPF를 설계하였다. $2.4{\times}2.0 (mm)$ 크기의 LTCC chip 형태로 제작하기위하여 LPF-HPF 형태를 응용한 집중소자형 Balun을 설계하고 Comb-line 형태의 BPF를 접합하여 설계 및 시뮬레이션을 하였다. 시뮬레이션 결과 Balun BPF의 삽입손실은 3.03dB, 위상차는 $170^{\circ}$, Amplitude balance는 0.09dB이다.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.09a
• /
• pp.65-89
• /
• 2003

Next Highly sophisticated communication generation of the Advanced Electronics and Imaging processing society will require a vast information volume and super high speed signal transport and information instruction. This means that super high technology should be created for satisfying the demand. It's also required the high reliability of the communication system itself, It will be supported the new advanced packaging technology of the 3 Dimensional structured system and system integration technology. Here is introduced the new 3 Dimensional technology for IC nnd LSI packaging and Opt-electronics Packaging of ASET activity in Japan.

• Journal of the Korean institute of surface engineering
• /
• v.54 no.5
• /
• pp.207-212
• /
• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.3
• /
• pp.53-58
• /
• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• Design & Manufacturing
• /
• v.10 no.3
• /
• pp.1-7
• /
• 2016

In the semiconductor industry the memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. After injection molding process the side gates were needed to remove for further assembly process. ln this study, the cold press cutting process was applied to remove the gates. For design of punch and die, the cold press cutting analysis was implemented by$DEFORM-2D^{TM}$ ln consideration of the simulation results, an adequate punch and die was designed and made for the cutting unit. In order to verify the performance of cutting process, the roughness of cutting section of the part was measured and was satisfied in requirement.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.7
• /
• pp.103-110
• /
• 2014

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.236-244
• /
• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of electromagnetic engineering and science
• /
• v.12 no.4
• /
• pp.234-239
• /
• 2012

This paper presents a compact K-band Doppler radar sensor for human vital signal detection that uses a radar configuration with only single coupler. The proposed radar front-end configuration can reduce the chip size and the additional RF power loss. The radar front-end IC is composed of a Lange coupler, VCO, and single balanced mixer. The oscillation frequency of the VCO is from 27.3 to 27.8 GHz. The phase noise of the VCO is -91.2 dBc/Hz at a 1 MHz offset frequency, and the output power is -4.8 dBm. The conversion gain of the mixer is about 11 dB. The chip size is $0.89{\times}1.47mm^2$. The compact Ka-band Doppler radar system was developed in order to demonstrate remote human vital signal detection. The radar system consists of a Ka-band Doppler radar module with a $2{\times}2$ patch array antenna, baseband signal conditioning block, DAQ system, and signal processing program. The front-end module size is $2.5{\times}2.5cm^2$. The proposed radar sensor can properly capture a human heartbeat and respiration rate at the distance of 50 cm.