• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.9-14
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• 2016

In the holographic data storage system, the data can be stored more than one bit per pixel and the storage capacity and transmission rate can be increased. In this paper, we proposed a sparse-ON pixel 4/6 balanced-modulation code that the code rate is 1.33 (bit/pixel) with uniform page density. Even though the performance of the proposed sparse-ON pixel 4/6 balanced-code is similar to 2/3 and 6/9 modulation codes, it can increase the storage capacity more than these modulation codes and also store more pages in a volume by reducing the rate of ON pixels to mitigate IPI (inter-page interference).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.607-613
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• 2008

In this paper, we investigate the performance of SMP-assisted 3GPP GERAN evolution system employing high order modulation and turbo coding. When applying the SMP which maps systematic bits into highly reliable bit positions, it is confirmed that there is the performance gain for the modulation and coding schemes of 16QAM(DAS-8) as well as 32QAM(DAS-11) by link level simulation.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.403-405
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• 2007

This paper presents the over-modulation strategy and indirect vector control drive of NPC type PWM inverter. NPC inverter has three level phase voltage output.It can perform in high voltage through assembling switching components. It has less harmonics and surge voltage stress at motor terminals than the 2 level inverter in same switching frequency through 3 level voltage. The conventional railway vehicle has used the vector control to MI=0.907 and the slip-frequency control from MI=0.907 to six-step mode. The slip-frequency control has bad motive power and slow torque control response. But vector control has good motive power and can instant torque control. In this paper, output voltage is controlled linearly from linear region to six-step mode by using over-modulation strategy. And NPC inverter is used.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1135-1141
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• 2007

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.3
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• pp.581-586
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• 2017

The well-known Integral Pulse Frequency Modulation (IPFM) cardiac oscillator has been used to generate the heart beat fluctuations as a representation of the modulatory autonomic nervous activity in terms of sympathetic and parasympathetic state. The IPFM model produces heartbeats by integrating the modulated sinusoid signals and applying the threshold of unity or chaotic threshold levels. This study aims at evaluating the performance of IPFM model by analyzing the influence of the threshold level with comparatively applying preset threshold of unity and Logistic-map and Henon-map chaotic-threshold. Based on our simulated results with interpreting the spectral features of Heart Rate Variability (HRV), we can conclude that the IPFM model with preset threshold level of unity can generate the optimal heartbeat variations int the sense of clinically valid heartbeats.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.2
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• pp.157-163
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• 1990

The PWM inverter investigated in this paper utilizes a bridge type current sharing reactor circuit with tow pairs of complementary transistor at each phase. The driving signals for this inverter are 3 level PWM waves of W type an M type modulation, which are obtained from a microprocessor based on the switching time data obtained by switching position calculation of triangular and sine modulation wave. The output voltage waveforms of this inverter have 5 level phase voltage and 9 level line voltage of PWM. The harmonics of the output voltage are reduced to half when it is compared with single CTI, and the occurrence of harmonics is also reduced.

• Proceedings of the Optical Society of Korea Conference
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• 1990.02a
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• pp.73-78
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• 1990

1.3${\mu}{\textrm}{m}$ DFB with absorption grating of 1.55${\mu}{\textrm}{m}$ InGaAsP layer was fabricated. This new type of DFB laser shows self-plusation for DC operation. At low level of injection the relation between the pulsation frequency and the injection current shows similar behavior with the relaxation oscillation of ordinary laser and at high level of injection the pulsation frequency decreases compared to the relaxation oscillation. Period doubling, period 3 and 4 were observed for AC modulation. In case of period doubling the waveform shows only one pulse within a period without any accompanying subsidiary pulses and the oscillation frequency was quite stable. The pulse widths as short as 58.5 ps was achieved with AC modulation. We propose the time division multiplexing application of this kind of DFB laser.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.2
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• pp.80-88
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• 1988

As a method to improve harmonics in the voltage source PWM inverter, 5 level stair case wave method is used. The complementary transistor inverter (CTI) bridge circuit has this characteristics. This circuit required synchronous type 3 level PWM signal. In this paper, the 3 phase PWM digital signals within about 10 modulation error of the natural sampling was caculated, and a ROM table out of it for the digital signal of the control system was made. According to this table, the digital control method was proposed, and DTI circuit operated by this method was reviewed. It was confirmed to make V/F control possible by the select modulation ratio to the frequency.

• Journal of Power Electronics
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• v.17 no.3
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• pp.653-663
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• 2017

Multilevel active neutral-point-clamped (ANPC) converter combines the advantages of three-level ANPC converter and multilevel flying capacitor (FC) converter. However, multilevel ANPC converter often suffers from capacitor voltage balancing problems. In order to solve the capacitor voltage balancing problems for five-level ANPC converter, phase-shifted pulse width modulation (PS-PWM) is used, which generally provides natural voltage balancing ability. However, the natural voltage balancing ability depends on the load conditions and converter parameters. In order to eliminate voltage deviations under steady-state and dynamic conditions, the active voltage-balancing control (AVBC) methods of floating capacitors and dc-link capacitors based on PS-PWM are proposed. First, the neutral-point current is regulated to balance the neutral-point voltage by injecting zero-sequence voltage. After that, the duty cycles of the redundant switch combinations are adjusted to balance the floating-capacitor voltages by introducing moderating variables for each of the phases. Finally, the effectiveness of the proposed AVBC methods is verified by experimental results.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.263-269
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• 2018

In this study, a selective inverter operation between a 2-level voltage source converter (VSC) and a 3-level T-type VSC (3LT VSC) is proposed to improve the efficiency of a 3LT VSC. The 3LT VSC topology, except for its neutral-point switches, has similar operations as that of the 2-level VSC. If an operation mode is changed according to efficiency, the efficiency can be improved because efficiencies of each methods are depending on current and MI (Modulation Index). The proposed method calculates the power losses of the two topologies and operates as the having lower losses. To calculate the losses, the switching and conduction losses based on the operation mode of each topology were analyzed. The controller determined the operation mode of the 2- or 3-level VSC based on the power loss calculated during every cycle. The validity of the proposed control scheme was investigated through simulation and experiments. The waveform and average efficiency of each method were compared.