• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.347-350
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• 2000

This paper deals with the novel DPWM(discontinuous PWM) for 3-level inverter. Although DPWM methods generate higher harmonics than SVPWM they are of special interest because of their lower switching losses. And in the high modulation region the harmonic characteristics of DPWM is superior to the that of CPWM. However when DPWM applies to the 3-level inverter there is the problem that the output state is varied suddenly in the low modulation region($\textrm{m}_{I}$=0~0.5) The novel DPWM that this problem improves will be introduced.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of Power Electronics
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• v.19 no.3
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.5
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• pp.51-56
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• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• Journal of Sensor Science and Technology
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• v.22 no.6
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• pp.421-427
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• 2013

In this paper, we introduce a new synchronous visible light communication system in which the synchronizing pulse and the data bits are simultaneously transmitted using a 3-level light signal. In the transmitter, the synchronizing pulse and the data bits modulate independently two identical visible LEDs, whose output lights add in free space, make 3-level optical signal. In the receiver, a photodiode detects the light and generates a 3-level output voltage, whose positive and negative part correspond to the synchronizing pulse and the data bits, respectively. The two signals are easily separated and recovered by a simple diode circuit. This configuration provides two independent VLC channels without any multiplexing technique, simplifies the circuit design and construction of synchronous VLC systems.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.129-130
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• 2016

본 논문에서는 근사 계단 제어 변조(Nearest Level Control Modulation)로 동작하는 모듈형 멀티레벨 컨버터(Modular Multi level Converter)에서 충전 회로나 반송파(Carrier)없이 초기 충전(Pre-charging)하는 새로운 방식을 제안하였다. 이의 성능을 검증하기 위해 PSCAD/EMTDC 소프트웨어를 통해 암(Arm)당 12개의 서브모듈(Sub-Module)로 구성된 3상 10kVA 모듈형 멀티레벨 컨버터를 구현 및 시뮬레이션을 수행하였다.

• Journal of Power Electronics
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• v.14 no.3
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• pp.531-540
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• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.10
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• pp.610-612
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• 2014

Mutilevel holographic data storage systems have a big advantage for capacity since it can store more than one bit per pixel. For instance, 2/3 modulation code stores 2/3(symbol/pixel) and 4/3(bit/pixel). Then it is about 1.3 bits per one pixel. In this paper, we propose two 4-level modulation codes, which have the minimum Euclidean distances of 3 and 4, respectively. The proposed codes perform better than random data. The performance of larger minimum distance code shows better than that of shorter one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.397-404
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• 2003

In this paper, we have analyzed the level of cross-modulation noise required for CDMA mobile station and proposed a guideline for optimum design. From the analysis, the level of cross-modulation noise is determined by the system's noise figure(NF) and VCO's phase noise and there is a trade-off relationships between them. In addition, we have determined the value of LNA's IIP3 and duplexer's isolation to satisfy the above level in designing the system. Therefore, this paper will give a guideline for a selection of components in designing cdma2000 mobile station.