• Journal of Ocean Engineering and Technology
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• v.35 no.3
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• pp.183-190
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• 2021

Tomographic particle image velocimetry (PIV) is a widely used method that measures a three-dimensional (3D) flow field by reconstructing camera images into voxel images. In 3D measurements, the setting and calibration of the camera's mapping function significantly impact the obtained results. In this study, a camera self-calibration technique is applied to tomographic PIV to reduce the occurrence of errors arising from such functions. The measured 3D particles are superimposed on the image to create a disparity map. Camera self-calibration is performed by reflecting the error of the disparity map to the center value of the particles. Vortex ring synthetic images are generated and the developed algorithm is applied. The optimal result is obtained by applying self-calibration once when the center error is less than 1 pixel and by applying self-calibration 2-3 times when it was more than 1 pixel; the maximum recovery ratio is 96%. Further self-correlation did not improve the results. The algorithm is evaluated by performing an actual rotational flow experiment, and the optimal result was obtained when self-calibration was applied once, as shown in the virtual image result. Therefore, the developed algorithm is expected to be utilized for the performance improvement of 3D flow measurements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.752-757
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• 2003

Recently, 3D structure recovery through self-calibration of camera has been actively researched. Traditional calibration algorithm requires known 3D coordinates of the control points while self-calibration only requires the corresponding points of images, thus it has more flexibility in real application. In general, self-calibration algorithm results in the nonlinear optimization problem using constraints from the intrinsic parameters of the camera. Thus, it requires initial value for the nonlinear minimization. Traditional approaches get the initial values assuming they have the same intrinsic parameters while they are dealing with the situation where the intrinsic parameters of the camera may change. In this paper, we propose new initialization method using the minimum 2 images. Proposed method is based on the assumption that the least violation of the camera’s intrinsic parameter gives more stable initial value. Synthetic and real experiment shows this result.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.10a
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• pp.345-346
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• 2006

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.391-394
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• 2005

In this paper, we present an approach that is able to reconstruct 3 dimensional metric models from un-calibrated images acquired by a freely moved camera system. If nothing is known of the calibration of either camera, nor the arrangement of one camera which respect to the other, then the projective reconstruction will have projective distortion which expressed by an arbitrary projective transformation. The distortion on the reconstruction is removed from projection to metric through self-calibration. The self-calibration requires no information about the camera matrices, or information about the scene geometry. Self-calibration is the process of determining internal camera parameters directly from multiply un-calibrated images. Self-calibration avoids the onerous task of calibrating cameras which needs to use special calibration objects. The root of the method is setting a uniquely fixed conic(absolute quadric) in 3D space. And it can make possible to figure out some way from the images. Once absolute quadric is identified, the metric geometry can be computed. We compared reconstruction image from calibrated images with the result by self-calibration method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.400-406
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• 2006

Knowledge of camera parameters, such as position, orientation and focal length, is essential to 3D information recovery or virtual object insertion. This paper analyzes the error sensitivity of focal length due to position error of feature points which are employed for self-calibration. We verify the dependency of the focal length on the distance from the principal point to feature points with simulations, and propose a criterion for feature selection to reduce the error sensitivity.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.3856-3863
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• 2012

A 3D reconstruction technique from stereo images that requires minimal intervention from the user has been developed. The reconstruction problem consists of three steps of estimating specific geometry groups. The first step is estimating the epipolar geometry that exists between the stereo image pairs which includes feature matching in both images. The second is estimating the affine geometry, a process to find a special plane in the projective space by means of vanishing points. The third step, which includes camera self-calibration, is obtaining a metric geometry from which a 3D model of the scene could be obtained. The major advantage of this method is that the stereo images do not need to be calibrated for reconstruction. The results of camera calibration and reconstruction have shown the possibility of obtaining a 3D model directly from features in the images.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.