• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 1997.11a
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• pp.29-29
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• 1997

각광 받는 구조재료인 섬유강화 복합적층재에 대한 기계적 체결 거동은 본질적인 재료의 이방성에 의해서 파단강도가 파단 모우드와 매우 밀접한 관련을 갖는 것으로 알려져 있다. 따라서, 복합적층판 체결부의 정밀 구조 설계에서는 단순화에 따른 오차를 줄이고 정밀해에 의한 설계 및 해석이 요청된다. 특히, 층간응력 성분을 무시할 수 없는 두께를 갖는 복합적층 판의 기계적 체결부 해석이나 실제 구조물의 체결부에서 발생하는 굽힘이나 비틀림과 같은 하중 상태를 묘사하기 위해서도 정밀한 3차원 응력 해석은 필요하다. 하지만, 지금까지 기계적 체결부의 거동에 관한 연구는 층간응력 성분들을 어느정도 무시할 수 있는 얇은 평판에 대한 2차원 응력해석에 주로 국한되어 왔으며, 일부 수행된 체결부에 대한 3차원 응력 해석의 경우 여러 단점을 갖는 3차원 연속체 요소에 의한 유한요소 해석이 수행되었을 뿐이다.본 연구는 층간응력 성분들을 무시할 수 없는 두께를 갖는 복합적층판의 기계적 체결부 해석에 지금까지 사용되어온 3차원 연속체 요소에 의한 유한요소 방법이 갖는 단점들을 개선한 Layerwise 유한요소법을 이용하여 3차원 응력해석을 수행하였다. 특히, 선형상보성원리에 근거한 최적설계 기법을 응용하여, 기계적 체결시 핀과 적층판의 홀 사이에 발생하는 하중 전달 과정을 모사하고, 접촉력에 의한 홀 주위의 복잡하고 국부적인 응력 집중현상을 규명하여본다.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.14 no.3
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• pp.299-308
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• 2001

This paper presents the three-dimensional (3-D) study of the natural vibration of cantilevered laminated composite plates. The Ritz method is used to obtain stationary values of the associated Lagrangian functional with displacements approximated by mathematically complete polynomials satisfying the boundary conditions at the clamped edge exactly. The accuracy of the 3-D model is established through a convergence study of non-dimensional frequencies followed by a comparison of the converged 3-D solutions with analytical and experimental findings in the existing literature. A wide scope of 3-D frequency results explain the influence of a number of geometrical and material parameters for cantilevered laminated plates, namely aspect ratio (a/b), width-to-thickness ratio (a/h), orthotropy of material, number of plies (NP), fiber orientation angle(θ), and stacking sequence.

• Journal of Power System Engineering
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• v.13 no.4
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• pp.49-55
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• 2009

복합재 적층판의 자유단 근처에서 나타나는 층간 응력의 집중 현상을 층간면 효과를 고려해 해석하였다. 복합재 적층판 내부의 임의의 위치에서 3차원 평형방정식을 만족시키기 위해 렉니츠키 응력함수를 도입하였으며, 가상일의 원리를 이용하여 지배방정식을 유도하였다. 주어진 응력함수를 이용하여 구한 3차원 응력들은 복합재 적층판의 아래 위 면뿐만 아니라 자유단에서 하중자유조건을 잘 만족한다. 기하학적 불연속성 때문에 복합재 적층판의 자유단에서는 응력의 특이가 발생하지만, 층간면 효과를 고려하게 되면 층간응력의 집중현상을 정확하게 해석할 수 있다. 자유단에서 발생한 층간응력의 크기를 보면, 층간면 효과를 고려할 경우, 응력특이 효과가 많이 줄어드는 것을 관찰할 수 있다. 본 연구에서 주어진 층간면에서의 정확한 응력 해석은 복합재 적층판의 강도설계를 수행하는 초기 설계 툴로 사용할 수 있다.

• Journal of the Korea institute for structural maintenance and inspection
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• v.11 no.3
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• pp.123-131
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• 2007

The buckling behavior of a fiber reinforced plastic pipe was researched. When a cylindrical structure is made of isotropic material, it shows two dimensional buckled shape which has same deformed section along the longitudinal direction. But an anisotropic cylindrical structure shows three dimensional buckled shape which has different deformed section along the longitudinal direction. Because the modulus of elasticity is varied in a certain direction when ply angles are changed, the strength of a pipe are changed as ply angles are changed. In this study, the limitation of two dimensional and three dimensional buckling mode was investigated and the buckling strength of a laminated composite pipe was evaluated.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.8
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• pp.881-886
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• 2014

The purpose of three-dimensional (3-D) metal printing using 5-axis is to deposit metal powder by changing the orientation of the deposited structure to be built for the overhang or undercut feature on part geometry. This requires a complicated preprocess functionality of providing three dimensionally sliced layers to cover the required part geometry. This study addresses the overhang/undercut problem in 3-D metal printing and discusses a possible solution of providing 3-D layers to be built using the DMT(R) machine.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.