• The Magazine of the IEIE
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• v.36 no.9
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• pp.51-60
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• 2009

• Journal of Welding and Joining
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• v.24 no.2
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• pp.10-16
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• 2006

본 논문에서는 전자 패키징의 고밀도 실장 프로세스와 관련하여 많은 연구와 개발이 이루어지고 있는 무연 솔더의 양산적용시의 문제점 침 도전성 접착제 및 3차원 패키징 기술과 신뢰성 평가방법 등을 개략적으로 소개하였다. 현재 국제적 규약에 의한 무연 솔더의 사용이 의무화되어 가고, 이에 따라 기존 솔더의 전기적 접속성, 열 도전성, 접합성 등의 특성을 확보하기 위한 새로운 재료 및 공정에 대한 연구 및 개발이 필요한 시점이다. 또한 기존의 접합 방법에서의 고집적화 및 미세 피치의 한계를 넘기 위한 3차원 패키징 기술 등이 시도되고 있다. 따라서 신소재 개발 및 공정 변화에 맞는 새로운 신뢰성 평가 방법의 도출도 필요하다. 아울러 국내 대학 및 관련 연구소에서도 국제 경쟁력을 향상시키고 차세대 첨단 산업 분야의 신기술을 확보하고 이를 선도하기 위한 체계적인 연구 활동이 요구된다.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.1-8
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• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.6
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• pp.923-931
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• 2013

RFID (Radio Frequency Identification), which is a kind of the electronic tag, is a wireless access device using the radio frequency for recognizing the ID information. It has a variety of application such as the bus card, gate access card, distribution industry, and management of construction materials. The performance and size of RFID depend on the penetrability, recognition ratio, memory size, multi tag recognition, external pollution dust, and exterior impact, and RFID requires the packaging to protect itself considered above factors. Recently, RFID is diversely employed to effectively manage construction materials and the RFID packaging, which is robust to the external impact, is required to attach RFID on construction materials. In this paper, we propose the construction material RFID packaging designed to be robust for the external impact and to be practicable for change of the broken RFID. For the change of RFID, we separate the cast and body of the packaging. Also, we present the detail drawing for the proposed construction material RFID packaging and implement the performance evaluation of the packaging manufactured using 3D printer.

• Electronics and Telecommunications Trends
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• v.25 no.5
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• pp.97-105
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• 2010

모바일과 유비쿼터스 센서 네트워크 센서 시대가 도래함에 따라 가볍고, 작고, 얇고, 멀티기능을 구현할 수 있는 부품에 대한 요구가 증대하고 있다. 이에 대한 여러 가지 솔루션 중 MCM의 개념을 수직 방향으로 확장시킨 3D IC가 최근 각광을 받고 있다. 이는 물리적인 한계에 부딪힌 반도체 집적 공정의 한계를 극복하여 지속적으로 무어의 법칙에 맞춰 집적도를 향상시킬 수 있을 뿐만 아니라 소재와 공정이 달라도 3차원적으로 집적이 가능하여 메모리와 프로세서로 대표되는 디지털 칩뿐만 아니라 아날로그/RF, 수동소자, 전력소자, 센서/액추에이터, 바이오칩 등을 하나로 패키징 할 수 있는 장점이 있기 때문이다. 이를 통해 성능 향상, 경박단소, 저비용의 부품 개발이 가능하기 때문에 미국, 유럽, 일본 등 선도국뿐만 아니라 싱가포르, 타이완, 중국 등에서도 활발한 연구가 진행되고 있으며 CMOS 이미지 센서 모듈 생산에 TSV 기술이 이미 적용되고 있다. 본 고에서는 3D IC를 위한 TSV 및 적층 요소 기술을 소개하고 이를 통해 개발된 사례와 표준화 동향에 대하여 소개하고자 한다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.1-16
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• 2023

Recently, the shift to next-generation wide-bandgap (WBG) power semiconductor for electric vehicle is accelerated due to the need to improve power conversion efficiency and to overcome the limitation of conventional Si power semiconductor. With the adoption of WBG semiconductor, it is also required that the packaging materials for power modules have high temperature durability. As an alternative to conventional high-temperature Pb-based solder, Ag sintering die attach, which is one of the power module packaging process, is receiving attention. In this study, we will introduce the recent research trends on the Ag sintering die attach process. The effects of sintering parameters on the bonding properties and methodology on the exact physical properties of Ag sintered layer by the realization 3D image are discussed. In addition, trends in thermal shock and power cycle reliability test results for power module are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.29-34
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• 2008

Generally, for conventional 3-D Hall sensor it is general that the sensitivity for $B_z$ is about 1/10 compared with those for $B_x$ or $B_y$. Therefore, in this work, we proposed 3-D Hall sensor with new structures. We have increased the sensitivity about 6 times to form the trench using anisotropic etching. And we have increased the sensitivity for the $B_z$ by 80 % compared with those of $B_x$ and $B_y$ using deposition of the ferromagnetic thin films on the bottom surface of the wafer to concentrate the magnetic fluxes. Sensitivities of the fabricated sensor with Ni/Fe film for $B_x,\;B_y$, and $B_z$ were measured as 361mV/T, 335mV/T, and 286mV/T, respectively. It has also showed sine wave of Hall voltages over a $360^{\circ}$ rotation. A packaged sensing part was $1.2{\times}1.2mm^2$. The measured linearity of the sensor was within ${\pm}3%$ of error. Resolution of the fabricated sensor was measured by $1{\times}10^{-5}T$.