• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.127-140
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• 2003

This paper develops a novel algorithm of computing 2 Dimensional Discrete Cosine Transform (2D-DCT) via Polynomial Transform (PT) converting 2D-DCT to the sum of 1D-DCTs. In computing N${\times}$M size 2D-DCT, the conventional row-column algorithm needs 3/2NMlog$_2$(NM)-2NM＋N＋M additions and 1/2NMlog$_2$(NM) additions and 1/2NMlog$_2$(NM) multiplications, while the proposed algorithm needs 3/2NMlog$_2$M＋NMlog$_2$N-M-N/2＋2 additions and 1/2NMlog$_2$M multiplications The previous polynomial transform needs complex operations because it applies the Euler equation to DCT. Since the suggested algorithm exploits the modular regularity embedded in DCT and directly decomposes 2D DCT into the sum of ID DCTs, the suggested algorithm does not require any complex operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.541-548
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• 2000

In the MPEG-4 standardization phase, many methods for coding the irregular shaped VOP (video object Plane) have been researched. Texture coding is one of interesting research items in the MPEG-4. There are the Low pass extrapolation (LPE) padding, the shape adaptive DCT (SA-DCT), and the Extension-Interpolation (EI)/2D-DCT proposed in [1] as texture coding methods. the EI/2D-DCT is the method extending and interpolating luminance values from and Arbitrarily Shaped (AS) image segment into an 8 x 8 block and transforming the extended and interpolated luminance values by the 8x8 DCT. although the EI/2D-DCT and the SA-DCT work well in coding the As image segments. they are degraded since they use one-dimensional (1-D) methods such as the 1D-EI and the 1D-DCT in the two-dimensional (2-D) space. in this paper, we analyze the performance of the EI/2D-DCTand propose a new non-symmetric sig-sag scanning method, which non-symmetrically scans the quantized coefficients in the DCT domain to improve the EI/2D-DCT.

• The Journal of Natural Sciences
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• v.7
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• pp.27-35
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• 1995

This paper introduces a VLSI (Very Large Scale Integrated Circuit) implementation of the 2-D Discrete Cosine Transform (DCT) with an application to image and video coding. This implementation, which is based upon a state space model, uses both algorithm and data partitioning to achieve high efficiency. With this implementation, the amount of data transfers between the processing elements (PEs) are reduced and all the data transfers are limitted to be local. This system accepts the input as a progressively scanned data stream which reduces the hardware required for the input data control module. With proper ordering of computations, a matrix transposition between two matrix by matrix multiplications, which is required in many 2-D DCT systems based upon a row-column decomposition, can be also removed. The new implementation scheme makes it feasible to implement a single 2-D DCT VLSI chip which can be easily expanded for a larger 2-D DCT by cascading these chips.

• Journal of Broadcast Engineering
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• v.26 no.5
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• pp.553-565
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• 2021

Point cloud is a set of points for representing a 3D object, and consists of geometric information, which is 3D coordinate information, and attribute information, which is information representing color, reflectance, and the like. In this way of expressing, it has a vast amount of data compared to 2D images. Therefore, a process of compressing the point cloud data in order to transmit the point cloud data or use it in various fields is required. Unlike color information corresponding to all 2D geometric information constituting a 2D image, a point cloud represents a point cloud including attribute information such as color in only a part of the 3D space. Therefore, separate processing of geometric information is also required. Based on these characteristics of point clouds, MPEG under ISO/IEC standardizes V-PCC, which imitates point cloud images and compresses them into 2D DCT-based 2D image compression codecs, as a compression method for high-density point cloud data. This has limitations in accurately representing 3D spatial information to proceed with compression by converting 3D point clouds to 2D, and difficulty in processing non-existent points when utilizing 3D DCT. Therefore, in this paper, we present 3D Discrete Cosine Transform-based Point Cloud Compression (3DCT PCC), a method to compress point cloud data, which is a 3D image by utilizing 3D DCT, and confirm the efficiency of 3D DCT compared to V-PCC based on 2D DCT.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1940-1943
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• 2003

본 논문은 Polynomial 변환을 이용하여 2차원 Discrete Cosine Transform (2D-DCT)의 계산을 1차원 DCT로 변환하여 계산하는 알고리즘을 개발한다. 기존의 일반적인 알고리즘인 row-column이 N×M의 2D-DCT에서 3/2NMlog₂(NM)-2NM＋N＋M의 합과 1/2NMlog₂(NM)의 곱셈이 필요한데 비하여 본 논문에서 제시한 알고리즘은 3/2NMlog₂M ＋NMlog₂N-M-N/2＋2의 합과 1/2NMlog₂M의 곱셈 수를 필요로 한다. 기존의 polynomial 변환에 의한 2D DCT는 Euler 공식을 적용하였기 때문에 복소 연산이 필요하지만 본 논문에서 제시한 polynomial 변환은 DCT의 modular 규칙을 이용하여 2D DCT를 ID DCT의 합으로 직접 변환하므로 복소 연산이 필요하지 않다. 또한 본 논문에서 제시한 알고리즘은 각 차원에서 데이터 크기가 다른 임의 크기의 2차원 데이터 변환에도 적용할 수 있다.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.157-160
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• 2003

In this paper. we propose a simple and effective video scene change detection algorithm using a 3-D DCT. The 3-D DCT that we employ is a 2$\times$2$\times$2 DCT has simple computations composed only of adding and shifting operations. The simple average values of multiresolution represented video using the 2$\times$2$\times$2 DCT are used as a detection feature vector.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5C
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• pp.461-467
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• 2003

We propose an efficient method for separable symmetric linear filtering in the DCT domain. First, separable 2-D linear filtering is decomposed into the cascade of 1-D filtering in the DCT domain. We investigate special characteristics of DCT domain filtering matrices when the filter coefficients are symmetric. Then we present the DCT domain 2-D filtering method using these characteristics. The proposed method requires smaller number of multiplications including typical sparseness of DCT coefficients compared to previous DCT domain linear filtering methods. Also, the proposed method is composed of simple and regular operations, which would be appropriate for efficient VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.