• Smart Media Journal
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• v.6 no.3
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• pp.9-14
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• 2017

This paper is a study on the hardware implementation of the encryption and decryption block of the lightweight block cipher algorithm LEA which can be used for tiny devices in IoT environment. It accepts all secret keys with 128 bit, 192 bit, and 256 bit sizes and aims at the integrated implementation of encryption and decryption functions. It describes design results of applying pipeline method for performance enhancement. When a decryption function is executed, round keys are used in reverse order of encryption function. An efficient hardware implementation method for minimizing performance degradation are suggested. Considering the number of rounds are 24, 28, or 32 times according to the size of secret keys, pipeline of LEA is implemented so that 4 round function operations are executed in each pipeline stage.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.249-254
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• 2008

The objective of this study is the developement of real time automatic incline measurement using high accuracy digital datalogger for safety and maintence of railway construction sites. For the replacement of current 16 bit analog/digital converter, Digital datalogger system using 24 bit analog/digital converter is studied for the first time with in a country. Therefore data communication method and analyzing program of automatic measurement data is developed for the automatic high accuracy digital datalogge system. The results of this study will be using real time automatic incline measurement of railway structures.

• Journal of the Chungcheong Mathematical Society
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• v.24 no.4
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• pp.927-934
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• 2011

Invertible transformations over n-bit words are essential ingredients in many cryptographic constructions. When n is large (e.g., n = 64) such invertible transformations are usually represented as a composition of simpler operations such as linear functions, S-P networks, Feistel structures and T-functions. Among them we study T-functions which are probably invertible and are very useful in stream ciphers. In this paper we study some conditions on a T-function h(x) such that f(x) = x + h(x) has a single cycle on ${\mathbb{Z}}_{2^n}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.49-54
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• 2007

As digital contents based on 3D graphics are increased, the requirement for low power 3D graphic hardware for mobile devices is increased. We design a transformation engine for mobile 3D graphic processor. We propose a simplified transformation engine for mobile 3D graphic processor. The area of the transformation engine is reduced by merging a mapping transformation unit into a projective transformation unit and by replacing a clipping unit with a selection unit. It consists of a viewing transformation unit a projective transformation unit a divide by w nit, and a selection unit. It can process 32 bit floating point format of the IEEE-754 standard or a reduced 24 bit floating point format. It has a pipelined architecture so that a vertex is processed every 4 cycles except for the initial latency. The RTL code is verified using an FPGA.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1132-1140
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• 1996

In video coding systems, an effective rate control method is one of the most improtant issues for the good video quality. This paper presents an adaptive rate control scheme based on the buffer fullness, quantization, and buffer utilization for very low bit rate communication lines, such as 16kbit/s, 24bit/s, and so on. The strategy is implemented on H.263, whichis a vide coding algorithm for narrow band telecommunication channels up to 64kbit/s recommended by ITU-T SG15, to show the effectiveness. The simulation result shows that the suggested rate control scheme has better SNR performance and buffer utilization of source coder than those of linear and non-linear[9] buffer control strategies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of Korean Tunnelling and Underground Space Association
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• v.3 no.4
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• pp.17-24
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• 2001

Four road tunnels of which the construction conditions were similar were selected in the paper, and laboratory tests and rockmass classification for the tunnels were carried out. And the analysis was performed to find out the correlation between ratio of bit abrasion or drilling parameter and support pattern of tunnel using jumbo drill machine. It was analyzed that there was average abrasion of bit from 11.85% to 3.25% per support patterns of tunnel in four tunnels. Drilling parameter happens to fluctuate according to extent of fracture zone.

• The Journal of the Acoustical Society of Korea
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• v.24 no.2E
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• pp.61-66
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• 2005

Experimental work in underwater acoustic communications using passive phase conjugation has shown that the demodulation error depends on the relative drift rate between the source and receiver [Rouseff et al., IEEE J. Oceanic Eng. 26, 821-831 (2001)]. The observed effect involves the mismatch between the initial impulse response and the subsequent response after the source or receiver has changed locations. In the present work, the effect of drifting source is analyzed by numerical simulations and compared to the experimental results. The communications bit error rate is qualified as a function of drift rate, drifting direction, and source-receiver range.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.833-840
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• 1987

A new Block Truncation Coding(BTC) technique reducing the bit-plane and using differential pulse code modulation (DPCM) is proposed and compared with the conventional BTC methods. A new technique decides whether the subblock can be approximated to be uniform or not. If the subblock can be approximated to be uniform(merge mode), we transmit only the gray-level informantion. It not (split mode), we transmity both the bit-plane and the gray-level information. DPCM method is proposed to the encoding of gray-level information when the subblock can be approximated to be uniform. Also modified quantization method is presented to the encoding of gray-level information when the subblock is not uniform. This technique shows the results of coding 256 level images at the average data rate of about 0.75 bits/pel.