JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low-Power ECC Check Bit Generator Implementation in DRAMs

  • Cha, Sang-Uhn (Department of Electronic and Electronics Engineering, Yonsei University) ;
  • Lee, Yun-Sang (Memory Division, Samsung Electronics) ;
  • Yoon, Hong-Il (Department of Electronic and Electronics Engineering, Yonsei University)
  • Published : 2006.12.31
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Abstract

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

Keywords

References

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