• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.87-93
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• 2010

This paper presents a high resolution, wide input range 2-step time-to-digital converter used in digital PLL. TDC is used to compare the DPLL output frequency with reference frequency and should be implemented with high resolution to improve the phase noise of DPLL. The conventional TDC consists of delay line realized inverters, whose resolution is determined by delay time of inverter and transistor size, resulting in limited resolution. In this paper, 2-step TDC with phase-interpolation and Time Amplifier is proposed to meet the high resolution and wide input range by implement the delay time less than an inverter delay. The gain of Time Amplifier is improved by using the delay time difference between two inverters. It is implemented in $0.13{\mu}m$ CMOS process and the die area is $800{\mu}m{\times}850{\mu}m$ Current consumption is 12 mA at the supply voltage of 1.2 V. The resolution and input range of the proposed TDC are 0.357 ps and 200 ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.10
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• pp.2554-2566
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• 1994

Robot position/force control has been a difficult task owing to the interaction between a robot and an environment with a rather high stiffness. In addition to the dynamic instability, the interaction causes the following problem : 1) chattering at steady-state, 2) dynamic coupling effect of robot, and 3) performance degradation due to a titled environment. To solve the problem, the Time Delay Control(TDC), which has been known to be quiet robust to plant uncertainties and disturbances, has been applied. In conjunction to TDC, the following three ideas were also used : 1) To reduce the amplitude of the chattering at the steady state, a novel scheme was adopted to enhance the resolution type solution of A/D conversion for the force sensor. 2) To reduce the dynamic coupling, a trajectory type position command was tried on a comparative basis to the step command, as well as a more accurate mass matrix was used instead of the constant mass matrix. 3) And finally to improve the performance in the tilted environment, force derivatives instead of position derivatives were used in the TDC law. Computer simulations and experiments resulted in obvious improvements on the quality of the hybrid control, thereby clearly demonstrating the effectiveness of TDC with the proposed ideas.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.2
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• pp.166-173
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• 1999

Reference models are used in many control algorithms for improvement of transient response characteristics. They provide desired trajectories that the plant should follow Most control systems have bounded control inputs to avoid saturation of the plant. If we design the reference models that do not account for limits of the control inputs, control performance of the system may be deteriorated. In this paper a new approach of avoiding saturation by varying the reference model for TDC(time delay control) based systems subject to step changes in the reference input. In this scheme, the variable reference model is determined based on the information on control inputs and the size of the step changes in the reference inputs. This scheme was verified by application to the BLDC motor position control system in simulations and experiments. The responses of the TDC with the variable reference model showed better tracking performance than that with the fixed reference model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.