• Title/Summary/Keyword: 2-stage interpolation

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Implementation and Verification of Linear Phase filter with Variable Cutoff Frequency for PCM/FM transmission (PCM/FM 전송을 위한 가변 컷오프 주파수 특성의 선형위상 필터 구현 및 검증)

  • Lee Sang-Rae;Ra Sung-Woong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.7C
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    • pp.713-724
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    • 2006
  • The purpose of this study is to design, implement and verify the pre-modulation filter with the variable -3dB cutoff frequency and linear phase response for bandlimiting the allocation of radio frequency bandwidth for PCM/FM transmission. For the design of this required filter, the digital FIR filter, DAC system and tuneable 2nd order LPF have been constructed and simulated according to the attenuation characteristic requirement of the amplitude frequency response by each stage. From these results, we have implemented the filter and verified the analog conversion hardware part which is composed of DAC system and tuneable 2nd order LPF for the interpolation of the discrete sequences. Especially this paper proposes and carries out the verification processes using the tone generator and the calibration procedures for more precise frequency response of the filter.

MULTI-SCALE MODELING AND ANALYSIS OF CONVECTIVE BOILING: TOWARDS THE PREDICTION OF CHF IN ROD BUNDLES

  • Niceno, B.;Sato, Y.;Badillo, A.;Andreani, M.
    • Nuclear Engineering and Technology
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    • v.42 no.6
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    • pp.620-635
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    • 2010
  • In this paper we describe current activities on the project Multi-Scale Modeling and Analysis of convective boiling (MSMA), conducted jointly by the Paul Scherrer Institute (PSI) and the Swiss Nuclear Utilities (Swissnuclear). The long-term aim of the MSMA project is to formulate improved closure laws for Computational Fluid Dynamics (CFD) simulations for prediction of convective boiling and eventually of the Critical Heat Flux (CHF). As boiling is controlled by the competition of numerous phenomena at various length and time scales, a multi-scale approach is employed to tackle the problem at different scales. In the MSMA project, the scales on which we focus range from the CFD scale (macro-scale), bubble size scale (meso-scale), liquid micro-layer and triple interline scale (micro-scale), and molecular scale (nano-scale). The current focus of the project is on micro- and meso-scales modeling. The numerical framework comprises a highly efficient, parallel DNS solver, the PSI-BOIL code. The code has incorporated an Immersed Boundary Method (IBM) to tackle complex geometries. For simulation of meso-scales (bubbles), we use the Constrained Interpolation Profile method: Conservative Semi-Lagrangian $2^{nd}$ order (CIP-CSL2). The phase change is described either by applying conventional jump conditions at the interface, or by using the Phase Field (PF) approach. In this work, we present selected results for flows in complex geometry using the IBM, selected bubbly flow simulations using the CIP-CSL2 method and results for phase change using the PF approach. In the subsequent stage of the project, the importance of effects of nano-scale processes on the global boiling heat transfer will be evaluated. To validate the models, more experimental information will be needed in the future, so it is expected that the MSMA project will become the seed for a long-term, combined theoretical and experimental program.

Verification of a novel fuel burnup algorithm in the RAPID code system based on Serpent-2 simulation of the TRIGA Mark II research reactor

  • Anze Pungercic;Valerio Mascolino ;Alireza Haghighat;Luka Snoj
    • Nuclear Engineering and Technology
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    • v.55 no.10
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    • pp.3732-3753
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    • 2023
  • The Real-time Analysis for Particle-transport and In-situ Detection (RAPID) Code System, developed based on the Multi-stage Response-function Transport (MRT) methodology, enables real-time simulation of nuclear systems such as reactor cores, spent nuclear fuel pools and casks, and sub-critical facilities. This paper presents the application of a novel fission matrix-based burnup methodology to the well-characterized JSI TRIGA Mark II research reactor. This methodology allows for calculation of nuclear fuel depletion by combination and interpolation of RAPID's burnup dependent fission matrix (FM) coefficients to take into account core changes due to burnup. The methodology is compared to experimentally validated Serpent-2 Monte Carlo depletion calculations. The results show that the burnup methodology for RAPID (bRAPID) implemented into RAPID is capable of accurately calculating the keff burnup changes of the reactor core as the average discrepancies throughout the whole burnup interval are 37 pcm. Furthermore, capability of accurately describing 3D fission source distribution changes with burnup is demonstrated by having less than 1% relative discrepancies compared to Serpent-2. Good agreement is observed for axially and pin-wise dependent fuel burnup and nuclear fuel nuclide composition as a function of burnup. It is demonstrated that bRAPID accurately describes burnup in areas with high gradients of neutron flux (e.g. vicinity of control rods). Observed discrepancies for some isotopes are explained by analyzing the neutron spectrum. This paper presents a powerful depletion calculation tool that is capable of characterization of spent nuclear fuel on the fly while the reactor is in operation.

High Frequency Noise Reduction in ECG using a Time-Varying Variable Cutoff Frequency Lowpass Filter (시변 가변차단주파수 저역통과필터를 이용한 심전도 고주파 잡음의 제거)

  • 최안식;우응제;박승훈;윤영로
    • Journal of Biomedical Engineering Research
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    • v.25 no.2
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    • pp.137-144
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    • 2004
  • ECG signals are often contaminated with high-frequency noise such as muscle artifact, power line interference, and others. In the ECG signal processing, especially during a pre-processing stage, numerous noise removal techniques have been used to reduce these high-frequency noise without much distorting the original signal. This paper proposes a new type of digital filter with a continuously variable cutoff frequency to improve the signal quality This filter consists of a cutoff frequency controller (CFC) and variable cutoff frequency lowpass filter (VCF-LPF). From the noisy input ECG signal, CFC produces a cutoff frequency control signal using the signal slew rate. We implemented VCF-LPF based on two new filter design methods called convex combination filter (CCF) and weight interpolation fille. (WIF). These two methods allow us to change the cutoff frequency of a lowpass filter In an arbitrary fine step. VCF-LPF shows an excellent noise reduction capability for the entire time segment of ECG excluding the rising and falling edge of a very sharp QRS complex. We found VCF-LPF very useful and practical for better signal visualization and probably for better ECG interpretation. We expect this new digital filter will find its applications especially in a home health management system where the measured ECG signals are easily contaminated with high-frequency noises .

Shape Optimal Design by P-version of Finite Element Method (p-Version 유한요소법에 의한 형상 최적화설계)

  • Kim, Haeng Joon;Woo, Kwang Sung
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.14 no.4
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    • pp.729-740
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    • 1994
  • In the shape optimal design based on h-version of FEM, the ideal mesh for the initial geometry most probably will not be suitable for the final analysis. Thus, it is necessary to remesh the geometry of the model at each stage of optimization. However, the p-version of FEM appears to be a very attractive alternative for use in shape optimization. The main advantages are as follows; firstly, the elements are not sensitive to distortion for interpolation polynomials of order $p{\geq}3$; secondly, even singular problems can be solved more efficiently with p-version than with the h-version by proper mesh design; thirdly, the initial mesh design are identical. The 2-D p-version model for shape optimization is presented on the basis of Bezier's curve fitting, gradient projection method, and integrals of Legendre polynomials. The numerical results are performed by p-version software RASNA.

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A STUDY ON A MULTI-LEVEL SUBSTRUCTURING METHOD FOR COMPUTATIONS OF FLUID FLOW (유동계산을 위한 다단계 부분 구조법에 대한 연구)

  • Kim J.W.
    • Journal of computational fluids engineering
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    • v.10 no.2
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    • pp.38-47
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    • 2005
  • Substructuring methods are often used in finite element structural analyses. In this study a multi-level substructuring(MLSS) algorithm is developed and proposed as a possible candidate for finite element fluid solvers. The present algorithm consists of four stages such as a gathering, a condensing, a solving and a scattering stage. At each level, a predetermined number of elements are gathered and condensed to form an element of higher level. At the highest level, each sub-domain consists of only one super-element. Thus, the inversion process of a stiffness matrix associated with internal degrees of freedom of each sub-domain has been replaced by a sequential static condensation of gathered element matrices. The global algebraic system arising from the assembly of each sub-domain matrices is solved using a well-known iterative solver such as the conjugare gradient(CG) or the conjugate gradient squared(CGS) method. A time comparison with CG has been performed on a 2-D Poisson problem. With one domain the computing time by MLSS is comparable with that by CG up to about 260,000 d.o.f. For 263,169 d.o.f using 8 x 8 sub-domains, the time by MLSS is reduced to a value less than $30\%$ of that by CG. The lid-driven cavity problem has been solved for Re = 3200 using the element interpolation degree(Deg.) up to cubic. in this case, preconditioning techniques usually accompanied by iterative solvers are not needed. Finite element formulation for the incompressible flow has been stabilized by a modified residual procedure proposed by Ilinca et al.[9].

A 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC with Various Circuit Sharing Schemes (다양한 회로 공유기법을 사용하는 10비트 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS Pipeline ADC)

  • Yoon, Kun-Yong;Lee, Se-Won;Choi, Min-Ho;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.4
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    • pp.53-63
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    • 2009
  • This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

A Calibration-Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High-Matching 3-D Symmetric Capacitors (높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기)

  • Moon, Kyoung-Jun;Lee, Kyung-Hoon;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.55-64
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    • 2006
  • This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

Design and Implementation of AR Model based Automatic Identification and Restoration Scheme for Line Scratches in Old Films (AR 모델 기반의 고전영화의 긁힘 손상의 자동 탐지 및 복원 시스템 설계와 구현)

  • Han, Ngoc-Soc;Kim, Seong-Whan
    • The KIPS Transactions:PartB
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    • v.17B no.1
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    • pp.47-54
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    • 2010
  • Old archived film shows two major defects: line scratch and blobs. In this paper, we present a design and implementation of an automatic video restoration system for line scratches observed in archived film. We use autoregressive (AR) image model because we can make stochastic and specifically autoregressive image generation process with our PAST-PRESENT model and Sampling Pattern. We designed locality maximizing scanning pattern, which can generate nearly stationary time-like series of pixels, which is a strong requirement for a stochastic series to be autoregressive. The sampled pixel series undergoes filtering and model fitting using Durbin-Levinson algorithm before interpolation process. We designed three-stage film restoration system, which includes (1) film acquisition from VHS tapes, (2) simple line scratch detection and restoration, and (3) manual blob identification and sophisticated inpainting scheme. We implemented film acquisition and simple inpainting scheme on Texas Instruments DSP board TMS320DM642 EVM, and implemented our AR inpainting scheme on PC for sophisticated restoration. We experimented our scheme with two old Korean films: "Viva Freedom" and "Robot Tae-Kwon-V", and the experimental results show that our scheme improves Bertalmio's scheme for subjective quality (MOS), objective quality (PSNR), and especially restoration ratio (RR), which reflects how much similar to the manual inpainting results.

A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter (14b 100MS/s $3.4mm^2$ 145mW 0.18un CMOS 파이프라인 A/D 변환기)

  • Kim Young-Ju;Park Yong-Hyun;Yoo Si-Wook;Kim Yong-Woo;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.54-63
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    • 2006
  • This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.