• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1019-1024
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• 2012

In this paper, a UWB antenna using a SIR(Step Impedance Resonator) that eliminate signal interference at 5 GHz WLAN as the first rejection band and adjust the second rejection band is proposed. Unlike the unit impedance resonator, the second harmonic of SIR is decided according to step impedance. Therefore, To adjust the second rejection band, SIR is applied to UWB antenna. Also, the equivalent circuit of the antenna at first rejection band is presented and the equivalent modeling values of the SIR and the coupling value is obtained. The proposed antenna is satisfied to cover full UWB band with return losses less than -10 dB and has band rejection characteristic in 5 GHz WLAN band. The radiation patterns show +y directivity characteristics in H-plane and the group delay variations are within 1.0 ns.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.461-473
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• 2003

Multimedia applications are much more sensitive to QoS(Quality of Service) than text based ones due to their data continuity. In order to provide a fast moving MH(Mobil Host) using multimedia application with a consistent QoS,an efficient call admission mechanism is in need. This paper proposes the 2SCA(2-Step Call Admission) scheme based on cal admission scheme using pripority to guarantee the consistent QoS for mobile multimedia applications. A calls of MH are classified new calls, hand-off calls, and QoS upgrading calls. The 2SCA is composed of the basic call admission and advanced call admission; the former determines the call admission based on bandwidth available in each cell and the latter determines the call admission by applying DTT(Delay Tolerance Time), PQeueu(Priority Queue), and UpQueue(Upgrade Queue) algorithm according to the type of each call blocked at the basic call admission stage. In order to evaluate the performance of our mechanism, we measure the metrics such as the dropping probability of new calls, dropping probability of hand-off calls, and bandwidth utilization. The result shows that the performance of our mechanism is superior to that of existing mechanisms such as CSP(Complete Sharing Policy), GCP(Guard Channel Policy) and AGCP(Adaptive Guard Channel Policy).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1355-1363
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• 2015

In order to maintain customer voltage within allowable limit($220{\pm}13V$), tap operation of SVR(step voltage regulator) installed in primary feeder could be carried out according to the scheduled delay time(30 sec) of SVR. However, the compensation of BESS(battery energy storage system) is being required because the customer voltages during the delay time of SVR have a difficultly to maintain within allowable limit when PV system is interconnected with primary feeder. Therefore, this paper presents modeling of SVR to regulate voltage with the LDC(line drop compensation) method and modeling of BESS to control active and reactive power bi-directionally. And also, this paper proposes the coordination control modeling between BESS and SVR in order to overcome voltage problems in distribution system. From the simulation results based on the modeling with the PSCAD/EMTDC, it is confirmed that proposed modeling is practical tool for voltage regulation analysis in distribution system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.213-221
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• 2004

A new method for design of two-channel finite-impulse response(FIR) quadrature mirror-image filter(QMF) banks with low reconstruction delay using weighting function is proposed. The weighting function used in this paper is calculated from the previous updated filter coefficients vector which is adjusted from iteration to iteration in the design of QMF banks. In this paper, passband and stopband edge frequency are used in design of QMF banks with low delay characteristic in time domain instead of specific frequency interval where the artifacts occur in conventional design method. The investigation of specific frequency interval where artifacts occur can not be required by using passband and stopband edge frequency. Some comparisons of performance are made with other existing design method to demonstrate the proposed method for QMF bank design. and it was observed that the proposed method using the weighted function and passband and stopband edge frequency improves the peak reconstruction error by 0.001 [dB], the peak-to-peak passband ripple by 0.003[dB], SNR with a white noise by 7[dB] and SNR with a step input by 32[dB], but with a reduction of the computational efficiency because of updating the weighting function over the conventional method in Ref [11].

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.2
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• pp.107-114
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• 2014

This paper applies a compensated low pass filter (LPF) to current measurements for permanent magnet synchronous motor (PMSM) drives. The noise limits the bandwidth of current controllers and has more adverse influences on control performances under the light load condition because of the low signal-to-noise ratio. In order to eliminate the noise sensitivity, this paper proposes a digital LPF with a compensator of gain attenuation and phase delay which are unacceptable in current information for PMSM drives. Characteristics of the proposed LPF are analyzed in comparison with the general LPFs. The compensated LPF is basically designed by the orthogonal property of the measured currents in the ${\alpha}{\beta}$ stationary reference frame. In addition, an implementation issue of the proposed method is discussed. Experimental results using the proposed method show improvements of the current control performance from two perspectives, rapid step responses and reductions of harmonic distortion.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1011-1016
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• 2020

Rapid change in network topology in high-speed VANET(: Vehicular Ad Hoc Network) is an important task for routing protocol design. Selecting the next hop relay node that affects the performance of the routing protocol is a difficult process. The disadvantages of AODV(: Ad Hoc On-Demand Distance Vector) related to VANET are end-to-end delay and packet loss. This paper proposes the AAODV (Advanced AODV) technique to reduce the number of RREQ (: Route Request) and RREP (: Route Reply) messages by modifying the AODV routing protocol and adding direction parameters and 2-step filtering. It can be seen that the proposed AAODV reduces packet loss and minimizes the effect of direction parameters, thereby increasing packet delivery rate and reducing end-to-end delay.

• Journal of The Korean Society of Agricultural Engineers
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• v.58 no.4
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• pp.21-35
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• 2016

This study is to evaluate the applicability of SWAT (Soil and Water Assessment Tool) model for multi-purpose dams and multi-function weirs operation in Namhan river basin ($12,577km^2$) of South Korea. The SWAT was calibrated (2005 ~ 2009) and validated (2010 ~ 2014) considering of 4 multi-purpose dams and 3 multi-function weirs using daily observed dam inflow and storage, evapotranspiration, soil moisture, and groundwater level data. Firstly, the dam inflow was calibrated by the five steps; (step 1) the physical rate between total runoff and evapotranspiration was controlled by ESCO, (step 2) the peak runoff was calibrated by CN, OV_N, and CH_N, (step 3) the baseflow was calibrated by GW_DELAY, (step 4) the recession curve of baseflow was calibrated by ALPHA_BF, (step 5) the flux between lateral flow and return flow was controlled by SOL_AWC and SOL_K, and (step 6) the flux between reevaporation and return flow was controlled by REVAPMN and GW_REVAP. Secondly, for the storage water level calibration, the SWAT emergency and principle spillway were applied for water level from design flood level to restricted water level for dam and from maximum to management water level for weir respectively. Finally, the parameters for evapotranspiration (ESCO), soil water (SOL_AWC) and groundwater level fluctuation (GWQMN, ALPHA_BF) were repeatedly adjusted by trial error method. For the dam inflow, the determination coefficient $R^2$ was above 0.80. The average Nash-Sutcliffe efficiency (NSE) was from 0.59 to 0.88 and the RMSE was from 3.3 mm/day to 8.6 mm/day respectively. For the water balance performance, the PBIAS was between 9.4 and 21.4 %. For the dam storage volume, the $R^2$ was above 0.63 and the PBIAS was between 6.3 and 13.5 % respectively. The average $R^2$ for evapotranspiration and soil moisture at CM (Cheongmicheon) site was 0.72 and 0.78, and the average $R^2$ for groundwater level was 0.59 and 0.60 at 2 YP (Yangpyeong) sites.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.