• Journal of Navigation and Port Research
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• v.26 no.1
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• pp.127-136
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• 2002

This paper Presents a discussion on the design and realization for the Phase Sensitive Defector (PSD) circuitry of Flu$\chi$-gate Compass that gives direction information to the Directional Frequency Analysis and Recording (DIFAR) Sonobuoy in Air Anti-Submarine Warfare. PSD circuitry is realized with Twin-T RC networked active band-pass filter. Results of a performance test the PSD circuitry shows that the effectiveness of band-pass filtering of desired $2F_0$ second harmonic signal, which is Pro- portional to the direction of earth's magnetic field. This resulted in the extraction of direction information.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.1-5
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• 2012

At the present time when the limits of the magnetic storage systems appear, the holographic data storage (HDS) devices with high data transfer rate and high recording density are emerging as attractive candidates for next-generation optical storage devices. In this paper, to effectively improve the detection performance that is degraded by the two-dimensional inter-symbol interference under the HDS channel environment and the pixel misalignment, an iterative two-dimensional equalization scheme is proposed based on the contraction mapping theorem. In order to evaluate the performance of the proposed scheme, for various holographic channel environments we measure the BER performance using computer simulation and compare the proposed one with the conventional threshold detection scheme, which verifies the superiority of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.57-63
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• 2001

The wound rotor type induction motor(WRIM) control system which is widely used in the industry has many maintenance problem because of external resistors and magnetic contactors. In this paper, the simple sensorless vector control algorithm for WRIM is proposed without any additional devices except detecting rotor currents. Because the external resistors are disconnectd and the rotor slip rings are shorten, the power loss due to external resistors is removed and the maintenance problem is improved remarkably. Also, the vector control performance becomes better because the proposed sensorless vector control algorithm does not use the rotor resistance which is usually used to estimate the slip frequency in case of indirect vector control scheme. The proposed algorithm is verified by the digital simulation and the experiment.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.18-24
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• 2010

A correct and accurate model of optical data storage systems is very important in development and performance evaluation of various data detection algorithms. In this paper, we present an nonlinear modeling scheme of a super-resolution near-field structure (Super-RENS) read-out signal using the canonical piecewise-linear (PWL) and the second-order Volterra models. Nonlinear equalizers may be developed on the basis of the information obtained from this nonlinear modeling. To mitigate the nonlinear inter-symbol interference (ISI), we proposed a new nonlinear equalizer for Super-RENS discs. Its validity is tested with the RF signal samples obtained from a Super-RENS disc. The experiment results verified the possibility that the canonical PWL and the second-older Volterra models can be utilized for nonlinear modeling of Super-RENS systems. The proposed equalizers are superior to the one without equalization in terms of bit error rate (BER).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.77-84
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• 2004

We design and implement the DSP module for automotive radar using FMCW. The designed parameters are based on 77GHz FMCW radar, and show the resolution of 0.4m and 0.67km/h in distance and velocity, respectively. For detecting multiple targets, we discuss the relationship between fb's and targets. In addition, we show that the detection of multiple targets is very simple when the range of $f_r$ is sufficiently larger than that of $f_b$. In the front of ADC, the 2nd order differentiator is applied for reducing the effects of path-loss so that the ADC bits are reduced to 8 bits. The designed block is simulated in Matlab and implemented with DSP and micro-processor.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.506-507
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• 2013

본 논문은 단상 전원 시스템에서 입력전원의 위상각 추정에 2차 일반화 적분기(Second-Order Generalized Integrator - SOGI)를 기반으로 하는 적응 필터구조를 적용한다. SOGI 출력은 전원 위상각과 관련되고, 올바른 출력을 위해서는 중심 주파수 ${\omega}^{\prime}$이 전원 주파수를 빠르게 추정할 수 있도록 FLL(Frequency Locked Loop)제어가 필요하다. SOGI-FLL의 기존의 방법과는 다르게 비선형 특성이 강한 주파수 동기화 동특성 모델에 퍼지제어를 적용함으로써 복잡한 선형화 과정이 필요하지 않으며, 실시간 이득 조절로 빠르게 전원 주파수 추정을 할 수 있는데 이는 최종적으로 빠른 전원 위상각 추정을 의미한다. 제안된 방법에 대해서 시뮬레이션을 통하여 그 타당성을 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.62-70
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• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.321-322
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• 2012

의료용 방사선 장비는 초기의 아날로그 방식의 필름 및 카세트에서 진보되어 현재는 디지털 방식의 DR (Digital Radiography)이 널리 사용되며 그에 관한 연구개발이 활발히 진행되고 있다. DR은 크게 간접방식과 직접방식의 두 분류로 나눌 수 있는데, 간접방식은 X선을 흡수하면 가시광선으로 전환하는 형광체(Scintillator)를 사용하여 X선을 가시광선으로 전환하고, 이를 Photodiode와 같은 광소자로 전기적 신호로 변환하여 방사선을 검출하는 방식을 말하며, 직접 방식은 X선을 흡수하면 전기적 신호를 발생 시키는 광도전체(Photoconductor)를 사용하여 광도전체 양단 전극에 고전압을 인가한 형태를 취하고 있는 가운데, X선이 조사되면 일차적으로 광도전체 내부에서 전자-전공쌍(Electron-hole pair)이 생성된다. 이들은 광도전체 양단의 인가되어 있는 전기장에 의해 전자는 +극으로, 전공은 -극으로 이동하여 아래에 위치한 Active matrix array을 통해 방사선을 검출하는 방식이다. 본 연구에서는 직접방식 X-ray 검출기에서 활용되는 a-Se을 ITO (Indium Thin oxide) glass 상단에 Thermal evaporation증착을 이용하여 두께 $50{\mu}m$, 33 넓이로 증착 시킨 다음, a-Se상단에 Sputtering증착을 이용하여 ITO를 11 cm, 22 cm, $2.7{\times}2.7cm$ 넓이로 증착시켜 상하부의 ITO를 Electrode로 이용하여 직접방식의 X-ray검출기 샘플을 제작하였다. 제작 과정 중 a-Se의 Thermal evaporation증착 시, 저진공 $310^{-3}_{Torr}$, 고진공 $2.210^{-5}_{Torr}$에서 보트의 가열 온도를 두 번의 스텝으로 나누어 증착 시켰다. 첫 번째 스텝 $250^{\circ}C$, 두 번째 스텝은 $260^{\circ}C$의 조건으로 증착하여 보트 내의 a-Se을 남기지 않고 전량을 소모할 수 있었으며, 스텝간의 온도차를 $10^{\circ}C$로 제어하여 균일한 박막을 형성 할 수 있었다. Sputtering증착 시, 저진공 $2.510^{-3}$, 고진공 $310^{-5}$에서 Ar, $O_2$를 사용하여 100 Sec간 플라즈마를 생성시켜 ITO를 증착하였다. 제작된 방사선 각각의 검출기 샘플 양단의 ITO에 500V의 전압을 인가하고, 진단 방사선 범위의 70 kVp, 100 mA, 0.03 sec 조건으로 X-ray를 조사시켜 ITO넓이에 따른 민감도(Sensitivity)와 암전류(Dark current)를 측정하였다. 측정결과 민감도(Sensitivity)는 X-ray샘플의 두께에 따른 $1V/{\mu}m$ 기준 시, 증착된 ITO의 넓이가 11 cm부터 22 cm, $2.7{\times}2.7cm$까지 각각 $7.610nC/cm^2$, $8.169nC/cm^2$, $6.769nC/cm^2$로 22 cm 넓이의 샘플이 가장 높은 민감도를 나타내었으나, 암전류(Dark current)는 $1.68nA/cm^2$, $3.132nA/cm^2$, $5.117nA/cm^2$로 11 cm 넓이의 샘플이 가장 낮은 값을 나타내었다. 이러한 데이터를 SNR (Signal to Noise Ratio)로 합산 하였을 시 104.359 ($1{\times}1$), 60.376($2{\times}2$), 30.621 ($2.7{\times}2.7$)로 11 cm 샘플이 신호 대 별 가장 우수한 효율을 나타냄을 알 수 있었다. 따라서 ITO박막의 면적이 클수록 민감도는 우수하나 그에 따른 암전류의 증가로 효율이 떨어짐을 검증 할 수 있었으며, 이는 ITO면적이 넓어짐에 따른 저항의 증가로 암전류에 영향을 끼침을 할 수 있었다. 본 연구를 통해 a-Se의 ITO 박막 면적에 따른 전기적 특성을 검증할 수 있었다.